1. Lecture 5. Sequential Logic 2 Prof. Taeweon Suh Computer Science Education Korea University 2010 R&E Computer System Education & Research

2. Korea Univ Clock Oscillators 2

3. Korea Univ Clock Oscillators in Digital Systems Virtually all digital systems are essentially operating synchronous to the clock 3

4. Korea Univ Where are Clock Oscillators? 4

5. Korea Univ Clock in Digital Circuit 5

6. Korea Univ Synchronous Sequential Logic Output of sequential logic is determined not only by current inputs but also by state stored in registers When sequential logic is working (updated) at the event (e.g., rising or falling edge) of clock source, we say that the circuit is synchronous to the clock  In other words, if the state is updated at the event of clock source, the circuit is synchronous sequential logic Virtually all digital systems are essentially synchronous to the clock  Virtually all digital systems are synchronous sequential logic 6

7. Korea Univ Synchronous Sequential Logic Synchronous sequential logic composition  Every circuit element is either a register or a combinational circuit  At least one circuit element is a register  All registers receive the same clock signal  Every cyclic path contains at least one register Two common synchronous sequential circuits  Finite state machines (FSMs)  Pipelines will talk in depth about pipeline in computer architecture class next semester 7

8. Korea Univ Finite State Machine (FSM) Finite state machines (FSMs) is composed of 2 components: registers and combinational logic  Registers represent one of the finite number of states k registers can represent one of a finite number (2 K ) of unique states An initial state (in registers) is assigned based on reset input at the (rising or falling) edge of clock  The next state may change depending on the current state as the next input comes in  Based on the current state (and input), output is determined via combinational logic 8

9. Korea Univ FSM Quick Example Vending machine  You are asked to design a vending machine to sell cokes. Suppose that a coke costs 300 won The machine takes only 100 won coins  How would you design a logic with inputs and output? 9 State 0 reset State 1 100 won State 2 100 won State 3 / coke out 100 won

10. Korea Univ Finite State Machine (FSM) FSM is composed of  State register that Store the current state Load the next state at the clock edge  Combinational logic that Computes the next state based on current state and input Computes the outputs based on current state (and input) 10

11. Korea Univ Finite State Machines (FSMs) Next state is determined by the current state and the inputs Two types of FSMs differ in the output logic  Moore FSM: outputs depend only on the current state  Mealy FSM: outputs depend on the current state and inputs 11

12. Korea Univ Moore and Mealy Edward F. Moore, 1925 - 2003  Together with Mealy, developed automata theory, the mathematical underpinnings of state machines, at Bell Labs.  Not to be confused with Intel founder Gordon Moore  Published a seminal article, Gedanken-experiments on Sequential Machines in 1956 George H. Mealy  Published “A Method of Synthesizing Sequential Circuits” in 1955  Wrote the first Bell Labs operating system for the IBM 704 computer 12

13. Korea Univ Finite State Machine Example Let’s design a simplified “traffic light controller”  Traffic sensors: T A, T B Each sensor becomes TRUE if students are present Each sensor becomes FALSE if the street is empty  Lights: L A, L B Each light receives digital inputs specifying whether it should be green, yellow, or red 13 Inputs: clk, Reset, T A, T B Outputs: L A, L B

14. Korea Univ FSM State Transition Diagram Moore FSM  Circles represent states  Arcs represent transitions between states  Outputs are labeled in each state 14 S0 L A : green L B : red S1 L A : yellow L B : red S2 L A : red L B : green S3 L A : red L B : yellow TATA Reset TATA TBTB TBTB

15. Korea Univ FSM State Transition Table 15 Current State Inputs Next State STATA TBTB S'S' S00X S1 S0 1 X S1X X S2 S3 X X X 0 1 X S2 S0

16. Korea Univ FSM Encoded State Transition Table 16 Current StateInputsNext State S1S1 S0S0 TATA TBTB S'1S'1 S'0S'0 000X01 001X00 01XX10 10X011 10X110 11XX00 StateEncoding S000 S101 S210 S311 S' 1 = S 1  S 0 S' 0 = S 1 S 0 T A + S 1 S 0 T B

17. Korea Univ FSM Output Table 17 Current StateOutputs S1S1 S0S0 LA1LA1 LA0LA0 LB1LB1 LB0LB0 OutputEncoding green00 yellow01 red10 L A1 = S 1 0 0 1 1 0 1 0 1 0 01 0 0 11 0 1 0 0 0 1 0 0 1 L A0 = S 1 S 0 L B1 = S 1 L B0 = S 1 S 0

18. Korea Univ FSM Schematic: State Register 18

19. Korea Univ FSM Schematic: Next State Logic 19 S' 1 = S 1  S 0 S' 0 = S 1 S 0 T A + S 1 S 0 T B

20. Korea Univ FSM Schematic: Output Logic 20 L A1 = S 1 L A0 = S 1 S 0 L B1 = S 1 L B0 = S 1 S 0

21. Korea Univ FSM Timing Diagram 21

22. Korea Univ FSM State Encoding In the previous example, the state and output encodings were selected arbitrarily  Different choice would have resulted in a different circuit Commonly used encoding methods  Binary encoding Each state is represented as a binary number  For example, to represent four states, we need 2 bits (00, 01, 10, 11)  One-hot encoding A separate bit is used for each state Only one bit is HIGH at once (one-hot)  For example, to represent four states, we need 4 bits (0001, 0010, 0100, 1000)  So, it requires more flip-flops But, it often results in simpler next state and output logic 22

23. Korea Univ Moore vs. Mealy FSM Two types of FSMs differ in the output logic  Moore FSM: outputs depend only on the current state  Mealy FSM: outputs depend on the current state and the inputs 23

24. Korea Univ Snail Example There is a snail  The snail crawls down a paper tape with 1’s and 0’s on it  The snail smiles whenever the last four digits it has crawled over are “1101” Design Moore and Mealy FSMs of the snail’s brain 24

25. Korea Univ State Transition Diagrams 25 Mealy FSM: arcs indicate input/output Moore FSM: arcs indicate input S0 0 reset S1 0 1 0 0 S2 0 1 1 S3 0 0 0 S4 1 1 1 0 S0 reset S1 1/0 0/0 S2 1/0 S3 0/0 1/1 1 11 1101101 (1101) 0/0

26. Korea Univ Moore FSM State Transition Table 26 Current State Inputs Next State SAS'S' S00 1 S1 0 S0 S1 S2 1 0 1 S3 S2 S3 S4 0 1 0 1 S0 S4 S0 S2

27. Korea Univ Moore FSM State Transition Table 27 Current StateInputsNext State S2S2 S1S1 S0S0 AS'2S'2 S'1S'1 S'0S'0 0000000 0001001 0010000 0011010 0100011 0101010 0110000 0111100 1000000 1001010 StateEncoding S0000 S1001 S2010 S3011 S4100 S' 2 = S 1 S 0 A S' 1 = S 1 S 0 A + S 1 S 0 + S 2 A S' 0 = S 2 S 1 S 0 A + S 1 S 0 A

28. Korea Univ Moore FSM Output Table 28 Current StateOutput S2S2 S1S1 S0S0 Y 000 001 010 011 100 Y = S 2 S0 S1 S2 S3 S4 0 0 0 0 1

29. Korea Univ Moore FSM Schematic 29 S' 2 = S 1 S 0 A S' 1 = S 1 S 0 A + S 1 S 0 + S 2 A S' 0 = S 2 S 1 S 0 A + S 1 S 0 A Y = S 2

30. Korea Univ Mealy FSM State Transition and Output Table 30 Current StateInputNext StateOutput S1S1 S0S0 AS'1S'1 S'0S'0 Y 000000 001010 010000 011100 100110 101100 110000 111011 StateEncoding S000 S101 S210 S311 S' 1 = S 1 S 0 + S 1 S 0 A S' 0 = S 1 S 0 A + S 1 S 0 A + S 1 S 0 A Y = S 1 S 0 A

31. Korea Univ Mealy FSM Schematic 31 S' 1 = S 1 S 0 + S 1 S 0 A S' 0 = S 1 S 0 A + S 1 S 0 A + S 1 S 0 A Y = S 1 S 0 A

32. Korea Univ Moore and Mealy Timing Diagram 32

33. Korea Univ Difference between Moore and Mealy FSMs A Moore machine typically has more states than a Mealy machine for a given problem A Mealy machine’s output rises a cycle sooner because it responds to the input rather than waiting for the state change  When choosing your FSM design style, consider when you want your outputs to respond 33

34. Korea Univ FSM Design Procedure Identify inputs and outputs Sketch a state transition diagram Write a state transition table Select state encodings For a Moore machine  Rewrite the state transition table with the selected state encodings  Write the output table For a Mealy machine  Rewrite the combined state transition table and output table with the selected state encodings Write Boolean equations for the next state and output logic Sketch the circuit schematic 34