1. A Low-Leakage 2.5GHZ Skewed CMOS 32-Bit Adder For Nanometer CMOS Technologies Advanced VLSI Course Seminar December 28, 2006 Peresented by: Rabe’e Majidi Advisor: Dr Mehdi Fakhraee Adopted: ISSCC 2005/Session20/Processor Building Blocks/20.4

2. 2 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

3. 3 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

4. 4 Leakage power control, why?  With technology scaling → leakage power of idle units becomes a large fraction of the total chip power [4].  Sub-threshold leakage power is soon expected to dominate the total power consumed by a CMOS circuit [2]. Fig.1. Power trends of high performance microprocessors [2].

5. 5 Charge Leakage CLCL Clk Out A MpMp MeMe Leakage sources CLK V Out Precharge Evaluate Dominant component is sub-threshold current Fig.2.Charge Leakage source, [3].

6. 6 Leakage power control methods The custom methods of Leakage power control [4]:  Dual threshold voltage  Dynamic sleep transistor  Body biasing techniques  Clock gating

7. 7 Using Dual threshold voltage Fig.3. Standard domino logic circuits. (a) Standard low-V t domino logic circuit. (b) Standard dual-V t domino logic circuit. High-V t transistors are symbolically represented by a thick line in the channel region [2].

8. 8 Using Dual threshold voltage  In a dual- domino circuit, all of the transistors that can be activated during the evaluation phase have a low-V t.  Alternatively, the precharge phase transitions are not critical for the performance of a domino logic circuit. Therefore, those transistors that are active during the precharge phase have a high-V t.  If all of the high-V t transistors are cutoff in a dual- domino logic circuit, the leakage current is significantly reduced as compared to a low-V t circuit.

9. 9 Dynamic Sleep transistors Fig.4.Sleep switch dual-Vt domino logic circuit technique. High-Vt transistors are symbolically represented by a thick line in the channel region [2].

10. 10 Body biasing techniques Fig.5.Transition based forward body biasing with low skew forward body bias [5].

11. 11 Clock gating Adopted : ISSCC 2003/Session6/Low power digital techniques/6.1/slides

12. 12 Active Leakage Control Adopted : ISSCC 2003/Session6/Low power digital techniques/6.1/slides

13. 13 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

14. 14 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

15. 15 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

16. 16 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

17. 17 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

18. 18 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

19. 19 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

20. 20 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

21. 21 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

22. 22 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

23. 23 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

24. 24 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

25. 25 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

26. 26 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

27. 27 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

28. 28 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

29. 29 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

30. 30 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

31. 31 Outline  Introduction  Leakage-optimized skewed-CMOS logic for circuit design-driven leakage reduction  Micro-architecture and data-path design - Modified 32b parallel-prefix adder architecture - Latches and flip-flops for Skewed CMOS logic  Measurement results of four adder cores using different 90nm CMOS device options, sleep transistor technique, and body biasing  Conclusion Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

32. 32 Adopted : ISSCC 2005/Session20/Processor Building Blocks/20.4/slides

33. 33 References [1] Klaus von Arnim, Peter Seegebrecht, Roland Thewes, Christian Pacha, Infineon Technologies, Munich, Germany,Christian Albrecht University, Kiel, Germany,” A Low- Leakage 2.5GHz Skewed CMOS 32b Adder for Nanometer CMOS Technologies”, ISSCC 2005/Session20/Processor Building Blocks/20.4,pp.380-381,Feb.,2005 [2] Volkan Kursun, Student Member, IEEE, and Eby G. Friedman, Fellow, IEEE, “ Sleep Switch Dual Threshold Voltage Domino Logic With Reduced Standby Leakage current” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 5, MAY 2004 [3] Jan.M.Rabaey, Anantha Chandraksan, Borivoje Nikolic, “Digital Integrated Circuits A Design Perspective”, Second Edition, 2005

34. 34 References [4] James Tschanz, Siva Narendra, Yibin Ye, Bradley Bloechel, Shekhar Borkar, Vivek De, Intel, Hillsboro, OR, “Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”, ISSCC 2003 / SESSION 6 / LOW-POWER DIGITAL TECHNIQUES / PAPER 6.1, pp. 102-103, Feb.,2003 [5] S. Jayapal and Y. Manoli, Chair of Microelectronics, Department of Microsystems Engineering (IMTEK), University of Freiburg, Georges-Koehler-Allee 102, 79110 Freiburg, Germany, “Monotonic transition based forward body bias for dual threshold voltage low power embedded processors”, Adv. Radio Sci., 4, 269–273, 2006, www.adv-radio-sci.net/4/269/006/ © Author(s) 2006. This work is licensed under a Creative Commons License.