1. CSE477 L07 Pass Transistor Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 07: Pass Transistor Logic Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477www.cse.psu.edu/~mji www.cse.psu.edu/~cg477 [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

2. CSE477 L07 Pass Transistor Logic.2Irwin&Vijay, PSU, 2003 Review: Static Complementary CMOS V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PUN and PDN are dual logic networks … …  High noise margins l V OH and V OL are at V DD and GND, respectively  Low output impedance, high input impedance  No static power consumption l Never a direct path between V DD and GND in steady state  Delay a function of load capacitance and transistor on resistance  Comparable rise and fall times (under the appropriate relative transistor sizing conditions)

3. CSE477 L07 Pass Transistor Logic.3Irwin&Vijay, PSU, 2003 Review: Static CMOS Full Adder Circuit B BB BB B B B A A A A A A A A C in !C out !Sum !C out = !C in (!A v !B) v !A !B C out = C in (A v B) v A B !Sum = C out (!A v !B v !C in ) v !A !B !C in Sum = !C out (A v B v C in ) v A B C in

4. CSE477 L07 Pass Transistor Logic.4Irwin&Vijay, PSU, 2003 NMOS Transistors in Series/Parallel  Primary inputs drive both gate and source/drain terminals  NMOS switch closes when the gate input is high  Remember - NMOS transistors pass a strong 0 but a weak 1 AB XY X = Y if A and B XY A B X = Y if A or B

5. CSE477 L07 Pass Transistor Logic.5Irwin&Vijay, PSU, 2003 PMOS Transistors in Series/Parallel  Primary inputs drive both gate and source/drain terminals  PMOS switch closes when the gate input is low  Remember - PMOS transistors pass a strong 1 but a weak 0 AB XY X = Y if A and B = A + B XY A B X = Y if A or B = A  B

6. CSE477 L07 Pass Transistor Logic.6Irwin&Vijay, PSU, 2003 Pass Transistor (PT) Logic A B F B 0  Gate is static – a low-impedance path exists to both supply rails under all circumstances  N transistors instead of 2N  No static power consumption  Ratioless  Bidirectional (versus undirectional) A 0 B B F

7. CSE477 L07 Pass Transistor Logic.7Irwin&Vijay, PSU, 2003 Pass Transistor (PT) Logic A B F B 0 A 0 B B = A  B F  Gate is static – a low-impedance path exists to both supply rails under all circumstances  N transistors instead of 2N  No static power consumption  Ratioless  Bidirectional (versus undirectional)

8. CSE477 L07 Pass Transistor Logic.8Irwin&Vijay, PSU, 2003 VTC of PT AND Gate A 0 B B F = A  B 0.5/0.25 1.5/0.25 B=V DD, A=0  V DD A=V DD, B=0  V DD A=B=0  V DD V out, V V in, V l Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)

9. CSE477 L07 Pass Transistor Logic.9Irwin&Vijay, PSU, 2003 Differential PT Logic (CPL) A B A B PT Network F A B A B Inverse PT Network F F F F=AB A A B B BB AND/NAND A A B F=A+B B BB OR/NOR A A F=A  B BB XOR/XNOR A A

10. CSE477 L07 Pass Transistor Logic.10Irwin&Vijay, PSU, 2003 CPL Properties  Differential so complementary data inputs and outputs are always available (so don’t need extra inverters)  Still static, since the output defining nodes are always tied to V DD or GND through a low resistance path  Design is modular; all gates use the same topology, only the inputs are permuted.  Simple XOR makes it attractive for structures like adders  Fast (assuming number of transistors in series is small)  Additional routing overhead for complementary signals  Still have static power dissipation problems

11. CSE477 L07 Pass Transistor Logic.11Irwin&Vijay, PSU, 2003 CPL Full Adder A A BB C in !Sum Sum C out !C out A A B B B BC in

12. CSE477 L07 Pass Transistor Logic.12Irwin&Vijay, PSU, 2003 CPL Full Adder A A BB C in !Sum Sum C out !C out A A B B B BC in

13. CSE477 L07 Pass Transistor Logic.13Irwin&Vijay, PSU, 2003 NMOS Only PT Driving an Inverter  V x does not pull up to V DD, but V DD – V Tn In = V DD A = V DD V x = V DD -V Tn M1M1 M2M2 B SD  Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from V DD to GND)  Notice V Tn increases for pass transistor due to body effect (V SB ) V GS

14. CSE477 L07 Pass Transistor Logic.14Irwin&Vijay, PSU, 2003 Voltage Swing of PT Driving an Inverter  Body effect – large V SB at x - when pulling high (B is tied to GND and S charged up close to V DD )  So the voltage drop is even worse V x = V DD - (V Tn0 +  (  (|2  f | + V x ) -  |2  f |)) In = 0  V DD V DD x Out 0.5/0.25 1.5/0.25 Time, ns Voltage, V In Out x = 1.8V D S B

15. CSE477 L07 Pass Transistor Logic.15Irwin&Vijay, PSU, 2003 Cascaded NMOS Only PTs B = V DD Out M1M1 y M2M2 Swing on y = V DD - V Tn1 - V Tn2 x M1M1 B = V DD Out y M2M2 Swing on y = V DD - V Tn1 C = V DD A = V DD C = V DD A = V DD l Pass transistor gates should never be cascaded as on the left l Logic on the right suffers from static power dissipation and reduced noise margins x = V DD - V Tn1 G S G S

16. CSE477 L07 Pass Transistor Logic.16Irwin&Vijay, PSU, 2003 Solution 1: Level Restorer  For correct operation M r must be sized correctly (ratioed) Level Restorer M1M1 M2M2 A=0 MnMn MrMr x B Out=1 off = 0 A=1 Out=0 on 1  Full swing on x (due to Level Restorer) so no static power consumption by inverter  No static backward current path through Level Restorer and PT since Restorer is only active when A is high

17. CSE477 L07 Pass Transistor Logic.17Irwin&Vijay, PSU, 2003 Transient Level Restorer Circuit Response Voltage, V Time, ps W/L r =1.75/0.25 W/L r =1.50/0.25 W/L r =1.25/0.25 W/L r =1.0/0.25 W/L n =0.50/0.25 W/L 2 =1.50/0.25 W/L 1 =0.50/0.25 node x never goes below V M of inverter so output never switches  Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f )

18. CSE477 L07 Pass Transistor Logic.18Irwin&Vijay, PSU, 2003 Solution 2: Multiple V T Transistors  Technology solution: Use (near) zero V T devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD )  Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V GS is below V T ) Out In 2 = 0V In 1 = 2.5V A = 2.5V B = 0V low V T transistors sneak path on off but leaking

19. CSE477 L07 Pass Transistor Logic.19Irwin&Vijay, PSU, 2003 Solution 3: Transmission Gates (TGs)  Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1 AB C C A B C C B C = V DD C = GND A = V DD B C = V DD C = GND A = GND  Most widely used solution

20. CSE477 L07 Pass Transistor Logic.20Irwin&Vijay, PSU, 2003 Solution 3: Transmission Gates (TGs)  Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1 AB C C A B C C B C = V DD C = GND A = V DD B C = V DD C = GND A = GND  Most widely used solution

21. CSE477 L07 Pass Transistor Logic.21Irwin&Vijay, PSU, 2003 TG Multiplexer GND V DD In 1 In 2 SS SS S S S In 1 F F F = !(In 1  S + In 2  S)

22. CSE477 L07 Pass Transistor Logic.22Irwin&Vijay, PSU, 2003 Transmission Gate XOR B A A  B

23. CSE477 L07 Pass Transistor Logic.23Irwin&Vijay, PSU, 2003 Transmission Gate XOR B A A  B 1 off an inverter B  !A 0 on weak 0 if !A weak 1 if A A  !B

24. CSE477 L07 Pass Transistor Logic.24Irwin&Vijay, PSU, 2003 TG Full Adder Sum C out A B C in

25. CSE477 L07 Pass Transistor Logic.25Irwin&Vijay, PSU, 2003 Differential TG Logic (DPL) A A B B B AND/NAND F=A  B XOR/XNOR A A B B A A B F=AB A A B BABA GND V DD B

26. CSE477 L07 Pass Transistor Logic.26Irwin&Vijay, PSU, 2003 Next Time: The MOS Transistor  MOS transistor dynamic behavior (R and C)  Wire capacitance

27. CSE477 L07 Pass Transistor Logic.27Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l MOS transistor dynamic behavior -Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5 l Wiring capacitance -Reading assignment – Rabaey, et al, 4.1-4.3.1  Reminders l HW#2 due September 30 th (Tuesday) l Project specs due (on-line) October 9 th l Evening midterm exam scheduled -Monday, October 20 th, 20:15 to 22:15, Location TBD -Only one midterm conflict scheduled