Designing with Transceiver-Based FPGAs at 40 nm

Name: Designing with Transceiver-Based FPGAs at 40 nm
Uploaded: 2017-08-14T11:32:23+00:00
Duration: PTM40S25
Channel: Tracey Cox
Description: Designing with Transceiver-Based FPGAs at 40 nm

Designing with Transceiver-Based FPGAs at 40 nm

Agenda Serial protocols introduction Signal integrity challenges
40-nm transceivers in FPGAs Protocol implementation examples PCI Express Gigabit Ethernet Conclusion

Serial Protocols Get Faster
FC16 10 OC192 10GE CEI-10G FC8 PCIe 3.0 Interlaken 6G CEI-6G XAUI FC4 PCIe 2.0 SRIO 3.125 SATA 2.0 PCIe 1.0 SRIO 2.5 3.072G OC48 2.4576G 3G SDI FC2 1.536G GPON Data rate (Gbps) in log scale GigE 1.2288G 1 FC1 SATA 1.0 SRIO 1.25 In 2002, serial protocols entered mainstream OBSAI 768M OC12 CPRI 614M HD-SDI SDI Mercury 2 ’01 1SGX 11 ’02 2SGX 3 ’06 AGX 6 ’07 4SGX 10’08 OC3 0.1 1985 1990 1995 2000 2005 2010 Protocol standard completion date

Signal Integrity Challenge
Electrical signal from point A needs to be delivered to point B Point A: TX - transmitter, we refer to near-end Point B: RX - receiver, we refer to far-end: either inside device (RX output) or right before RX pins Via Interconnect: Link (IO card+back-plane+IO card) A B near-end eye far-end eye TX RX RX output I/O card backplane connector transmit device receive device

Why the Challenge? Inside interconnect:
Incident  Attenuation + Reflection + Radiation + Coupling  Transmitted A B TX RX

Degradation is Proportional to Data Rate
0 dB is 100% -5 dB is 56% -10 dB is 32% Collection of customer backplane transfer functions -40 dB is 1% 3.125 Gbps 6.25 Gbps 8.5 Gbps -60 dB is 0.1% 10 Gbps

Pre-emphasis What are the benefits? What does it do?
Makes driving long traces and backplanes above Gbps possible Longer traces and/or faster data rates require more pre-emphasis What does it do? Transmitter compensates for channel degradation What issues does it solve? Relaxes layout constraints by allowing longer routing traces Allows legacy backplanes, designed for slower speeds, to run faster Improves signal integrity May be used with equalization Does this differentiate Altera from competition? At par for data rates below Gbps Clear advantage above Gbps Proven solution up to Gbps with transceiver block in Stratix® II GX FPGA

Pre-emphasis Opens Eye on 40” PCB @ 6 Gbps
3” PCB trace (FR-4 material) 40” PCB trace (FR-4 material) Increasing pre-emphasis levels Equivalent to driving a 6g

6.25-Gbps Signal Degrades Over 40” of PCB
3 ones, 5 zeroes 1 3 4 Short trace (5”) no pre-emphasis Long trace (40”) Not DC balanced 2 1 Short trace (5”) 4 3 2 Long trace (40”)

6.25-Gbps Signal Improves With Pre-emphasis
3 4 3 ones, 5 zeroes 1 Short trace (5”) with pre-emphasis Long trace (40”) DC balanced 2 Short trace (5”) 1 3 4 2 Long trace (40”)

Equalization What are the benefits? What does it do?
Make driving long traces and backplanes above Gbps possible Longer traces and/or faster data rates require more equalization What does it do? Receiver compensates for channel degradation What issues does this it solve? Relaxes layout constraints by allowing longer routing traces Allows legacy backplanes, designed for slower speeds, to run faster Improves signal integrity May be used with pre-emphasis Does this differentiate Altera from competition? At par for data rates below Gbps Clear advantage above Gbps Proven solution up to Gbps with transceiver block in Stratix II GX

+ = Types of Equalization
Since the interconnect is a linear system we can create an inverse transfer function at the receiver (equalize) to undo the effects of the interconnect There are two types of equalization Linear and DFE (Decision Feedback Equalizer) The end goal is to achieve a transfer function with a flat response in the frequency of interest + = Flat system response Equalizer Interconnect

Flat System Response = +   Equalizer Interconnect

Linear Equalizer Part of receiver input stage
FFE – Feed Forward Equalization (Linear) Advantage: Requires no prior data knowledge Disadvantage: amplifies crosstalk Equalizer OFF Equalizer ON RX output TX RX Near-end eye Far-end eye

Pre-emphasis and Equalization Link Estimator (PELE)
What are the benefits? Simulate links at a fraction of the time compared to HSPICE, save hundreds of hours Automatically derive optimal pre-emphasis and equalization settings What does it do? PELE is a MATLAB tool that takes transceiver models with s-parameter models of a link to simulate and automatically derive optimal pre-emphasis or equalization settings What issues does it solve? With PELE, engineers can move away from trial and error when determining optimal PE settings by using HSPICE alone There are a number of ways to extract s-parameters of a channel Cadence, Mentor, Agilent or Ansoft have tools that extract s-parameters from layout Agilent has network analyzers to extract s-parameters physical links Both Tek and Agilent have software that convert oscilloscope measurements into s-parameters Does this differentiate Altera from competition? Clear advantage for Altera PELE is available when using Mentor SI tools Competition has no PELE equivalent

Customer provided S-parameters
PELE: Proprietary EDA Tool Determines Pre-emphasis and Equalization Coefficients TX model Customer provided S-parameters RX model PELE Coefficients Backplane

Equalization Opens Eye Across 40” at 6.375 G
Simulated with PELE Eye without equalization Eye with equalization 17dB equalization

Plug & Play Signal Integrity (ADCE)
What are the benefits? Plug and play End backplane characterization or simulation, ADCE automatically and continuously adjusts equalizer for optimal signal integrity What does it do? ADCE is the acronym for Adaptive Dispersion Compensation Engine Receiver automatically and continuously adjusts equalizer settings for optimum signal integrity What issues does this it solve? Eliminates tedious task of finding optimal equalization settings through simulation and lab measurements which typically takes man weeks of time Does this differentiate Altera from competition? Clear advantage with Plug and Play signal integrity Competition has no ADCE equivalent

ADCE Altera developed ADCE
Automatically monitors and adjusts the receive equalizer for the best eye opening PVT continuously monitored and compensated Can be run continuously, on power up, or on demand Altera's adaptive equalizer (ADCE) automatically monitors and adjusts the receive equalizer for the best eye opening. Altera’s hot-socketable transceivers, coupled with ADCE technology, deliver Plug and Play Signal Integrity, in which you can design systems with truly universal cards that plug into multiple card positions in system backplanes Design with Altera and design with confidence, knowing that the manufacturing, materials, temperature, voltage and silicon process variations are being continuously monitored and compensated for by the ADCE to deliver the best eye opening and system BER performance.

Industry’s 1st 40-nm Transceiver
Building on a solid foundation at 40 nm

FPGA Layout (Stratix IV GX FPGA)
PCIe hard IP Blocks Transceiver, LVDS and GPIOs may be used concurrently – no restrictions Transceiver block, with four 8.5Gbps transceivers, and two 3.2Gbps transceivers High-Speed LVDS IO Banks with DPA capability

Transceiver Block CMU – clock multiplier unit

CMU Block in PMA-Only Mode

Transceiver Channel PMA + PCS PMA only mode Phase Comp FIFO Transmit
PIPE Byte serializer 8b/10b encoder Bit serializer Pre-emphasis Core logic or PCIe hard IP Phase Comp FIFO Receive PIPE Byte ordering Byte deserializer 8b/10b decoder Rate matcher Deskew FIFO Word aligner Bit deserializer CDR Equalizer Bit serializer Pre-emphasis Core logic Bit deserializer CDR Equalizer PMA only mode

Feature Comparison - Transceivers
Transceiver type PMA + PCS PMA only Full duplex Yes Pre-emphasis Equalization DFE No ADCE PCI Express PMA requirements 8b/10b Rate matcher Phase compensation FIFO PMA power Gbps 100 mW PMA power Gbps 135 mW 25 25

Protocol Support Protocol HardCopy® IV ASICs Stratix IV FPGAs 3G protocols PCI Express Gen1 (x1, x2, x4, x8), PCI Express cable  Serial RapidIO® (1x, 4x) Gigabit Ethernet, XAUI (IEEE 802.3ae), HiGig+ 3G basic (proprietary), 3G SerialLite II CPRI v3.0, OBSAI v2.0/RP3-01 v4.0 SONET OC-3/12/48, GPON SATA, SAS SD, HD and 3G SDI, ASI Serial data converter (JESD204) SFI 5.1 Up to 8 channels HyperTransport™ 3.0 6G protocols PCI Express Gen2 (x1, x2, x4, x8) HiGig2, CEI-6G (SR/LR), Interlaken, DDR-XAUI, SPAUI 6G basic (proprietary), 6G SerialLite II 6G CPRI/OBSAI Fibre Channel (FC1/FC2/FC4) Transceiver Type Stratix IV GX FPGAs HardCopy IV GX ASICs PCS + PMA 600 Mbps –8.5 Gbps Mbps –7+ Gbps Speed Grade - 2: 8.5 Gbps n/a (max data rate) - 3: Gbps - 4: 5.0 Gbps 26 26

Dynamic Reconfiguration
What are the benefits? Reduced cost when implementing multi-rate or multi-protocol systems Enable a single hardware to support multiple protocols What does it do? Dynamically reconfigure transceiver protocol mode at run time without interrupting adjacent transceivers What issues does it solve? End customers can provision an optical port for any serial protocol which previously required a different line card End customers to support different data rates on a backplane, slower data rates for legacy cards and faster for next-generation systems Does this differentiate Altera from competition? Clear differentiation due to transceiver block flexibility (2 clock inputs and inter block lines) Sophisticated dynamic reconfiguration MegaWizard® vs. primitive capability with Xilinx

Dynamically Optimize Signal Integrity
Change output differential voltage amplitude Optimize transmit pre-emphasis levels Optimize receive equalization levels Dynamic reconfiguration allows the user to optimize signal integrity by adjusting the differential output amplitude of the transmitter, select from thousands of combinations of pre-emphasis and equalization settings.

Dynamic Reconfiguration: Protocol and Rate
Multi-rate examples Fibre Channel: 1G, 2G, and 4G SONET/SDH: OC3, OC12, and OC48 SDI: SD, HD, and 3G PCI Express: 1.0, 2.0 Proprietary backplane or SerialLite II: Gbps and 6.25 Gbps Multi-protocol examples Multi-service provisioning platforms (MSPP) SONET, Fibre Channel, and Gigabit Ethernet Dynamic reconfiguration also allows designers to dynamically change the data rate for multi-rate applications. For example Fibre Channel 1G, 2G and 4G, SONET/SDH OC3, OC12 and OC48, Serial Digital Interface: Standard Definition, High Definition and 3G; PCI Express Gen 1 and 2. Dynamic reconfiguration also allows users to support faster rates on backplanes without having to obsolete legacy line cards. Dynamic reconfiguration also allows designers to dynamically change not only data rate but also the protocol. The Stratix II GX FPGA with dynamic reconfiguration can minimize the number of ASSPs required on a board and in some cases reduce the number of boards. With dynamic reconfiguration the transceiver becomes a universal front end that can support many different protocols dynamically without interruption to adjacent channels.

Dynamic Reconfiguration Example
Each PLL can select from multiple clock sources External clock Internal PLD clock Clock from adjacent transceiver block Each transceiver channel can select either PLL PLL0 or PLL1 Example: SONET and GigE Each transceiver can be dynamically configured for OC3, OC12, OC48 or GigE The embedded transceiver block in the Stratix II GX consists of 4 independent full duplex transceiver channels and a central block which includes the PLLs. The designer has the flexibility to select from different PLL clock sources including an external clock reference like a crystal oscillator, clock from the PLD fabric or clock from adjacent transceiver blocks via the Intra Quad lines or IQ lines. The designer also has the flexibility to select from one of two PLLs to clock each transceiver channel. The multiple data rate and protocol example shows dynamic reconfiguration being used to reconfigure each channel for a different data rate and protocol. The 3rd transceiver from the top is the midst of being reconfigured from GigE to OC48.

Dynamic Reconfiguration Block
One dynamic reconfiguration block is shared by up to 4 transceiver blocks MIFs (memory initialization file) store unique transceiver settings Vod, pre-emphasis and equalization settings data rate protocol settings input clock MIFs can be stored in on-chip or external memory locations Transceiver channels are modified via the dynamic reconfiguration block Dynamic reconfiguration is facilitated by the Quartus II S/W. One dynamic reconfiguration block can be shared by four transceiver blocks. The diagram shows 2 of the 4 maximum transceiver blocks being controlled by the dyanmic reconfiguration block (alt2_reconfig). Quartus II S/W generates MIF files which contain unique transceiver settings including; Vod, pre-emphasis & equalization settings; data rate and protocol settings. MIFs can be stored in on-chip or external memory locations.

PCI Express Implementation

Hard IP for PCI Express (Stratix IV GX FPGA)
Address ECC PLD fabric logic Non PCIe applications 1 Stratix 4 GX transceivers Soft IP PCIe protocol stack 2 Transaction layer Data link layer Phy MAC layer Quad 2 PCS PMA PCS PMA PCS PMA PCS PMA 3 Transaction layer over HIP TL bypass HIP bypass User application Quad 1 Transaction layer (= TL) Data link layer PHY MAC PCS PMA PCS PMA PCS PMA TL PCS PMA 4 PIPE-2.0 LMI (*) Parallel access Hard IP PCIe block DPRIO (**) Here is the block diagram. On the right you see the transceivers which also can be used for non PCI Express application. The interface to the hard IP block supports a PIPE 2.0 compliant interface. The hard IP PCI Express block offers support for endport and rootport applications and as you can see implements a complete protocol stack. If you need the flexibility, different layers can be bypassed as you can see in the block diagram, e.g. for application which need a custom solution for the transaction layer. Soft logic Non PCI Express cores (XAUI, GbE, SRIO, etc…) Soft PCI Express IP protocol stack Soft PCI Express IP transaction layer over hard IP DL and PHY MAC Hard Gen1/Gen2 x8, x4, x1 EP/RP hard IP (HIP) protocol stack PCIe hard IP PCS/PMA (*) LMI- Local Management Interface (**) DPRIO- Dynamic Partial Reconfigurable Input/Output

Hard IP Feature Set High-performance applications Feature rich
PCIe 1.1 / 2.0 compliant protocol stack Integrated TL, DLL, PHY, MAC layers 2 - 4 hard IP cores per device Feature rich x1, x4, x8 initial link width configurations x2 mode supported through down configuration 125- or 250-MHz application layer clock rate supported Configurable maximum payload size (128, 256, 512, 1024, 2048 bytes) 1 or 2 virtual channels 64-bit Avalon®-ST in all modes 128-bit Avalon-ST in Gen1 x8, Gen2 x4, and Gen2 x8

Physical coding sub-layer High-performance, feature-rich IP core
Soft IP Core Physical layer Physical coding sub-layer Upper protocol layers PCS PCI Express IP core x1 x4 x8 PIPE interface SERDES x1 PCS SERDES x1 PCS SERDES x1 PCS SERDES x1 Proven solution ~150 licenses issued PCI Express 1.1 compliance Extensive performance benchmarking data across multiple chipsets/platforms Additional interoperability with multiple ASSPs Flexible and feature rich Easy timing closure with support for incremental compilation Easy integration using SOPC Builder (x1, x4) Configurable maximum payload up to 2 Kbyte and configurable retry buffer Optional end-to-end cyclic redundancy code (ECRC) generation/checking and advanced error reporting (AER) Flexible reference clock support (100, 125, or MHz) High-performance, feature-rich IP core

10-Gigabit Ethernet Reference Design Features

10-Gigabit Ethernet Reference Design XAUI and XGMII Interfaces
Altera® FPGA (– GX) Standard PHY product 10-GbE reference design Network interface Avalon-ST 10-GbE MAC Mgmt. Hard PCS 10GBase-X (8b/10b) Hard PMA 10GBase-X (4 x Gbyte Tx) XAUI PMD, copper, or optical System interface Avalon-MM MDIO - MDC Mgmt. slave interface Altera FPGA Standard PHY product 10-GbE reference design Network interface Avalon-ST 10-GbE MAC Mgmt. XGMII 10-Gbyte PHY device System interface 32-bit @ MHz Avalon-MM MDIO - MDC Hard silicon Mgmt. slave interface Soft core

10-Gigabit Ethernet Reference Design
Configuration options 10-Gbps Ethernet MAC + hard PCS + XAUI PMA 10-GbE MAC with XGMII parallel interface Supported devices Stratix II, Stratix II GX, Stratix III, Stratix IV (prelim), and Arria® GX FPGAs

10-Gigabit Ethernet MAC Detailed Features Encapsulation
Full duplex operation supporting 10-Gbps Ethernet data rate IEEE 802.3ae Gbps Ethernet standards compliant Easy MegaWizard II user configuration software Transmitter (TX) data encapsulation and receiver (RX) de-capsulation Tx frame delimiting and Rx frame synchronization per Ethernet frame definition (IEEE clauses 3, 4, and Annex 4A) Preamble and start of frame delimiter (SFD) generation and detection MAC address and VLAN tag transparency Promiscuous (transparent) mode: No Tx source MAC address and FCS insertion and no Rx destination MAC and VLAN tag recognition/filtering and FCS removal Rx error frames still filtered Non-promiscuous mode: Tx source MAC address and FCS insertion and Rx destination MAC and VLAN tag filtering and FCS removal; broadcast address filtering in Rx Option: Rx address recognition and filtering  two destination MAC addresses, register configurable, and broadcast MAC address Transparently passing Tx frame length/type field and checking Rx frame Pad insertion and removal for shorter-than minimum-length frames No OC 192 support Promiscous mode is essentially no address matching. FCS forwarding is still available with its own config register FCS, not RCS Remove ‘1’ in front of broadcast

10-GbE MAC Detailed Features Encapsulation and Interfaces
Tx data encapsulation and Rx data de-capsulation (cont.) Tx 32-bit CRC (FCS) generation and insertion Tx incomplete frame terminate and recover Rx error detection: CRC, preamble, length format, and runt Rx error frame drop or pass-through; register configurable Configurable Tx inter-frame gap insertion range Minimum 64-bit times to dynamically adjust for Tx data rate adaptation to OC-192 or other data rates Deficit idle counter support Frame length range: 64 bytes to 16 KBytes super-jumbo Interfaces External XAUI XGMII Option: PHY device management  MDIO-MDC (compliant with IEEE clauses 45 and 22) Internal MAC datapath interface with PCS or serial transceiver: XGMII Internal system datapath: Avalon-Streaming bus, MHz, big endian Option: Tx and Rx FIFO, selectable size, configurable AF and AE flags Internal management (IP configuration and monitoring): Avalon-MM bus, 32-bit Internal PCS and serial transceiver management path: native internal management bus We support down to 64 bit (8 bytes) of inter frame gap The MDIO is compliant to both clause 22 and 45 The FIFO also provide a different clock for the user interface

10-GbE MAC Detailed Features Flow Control, Management, and Performance
Compliant with IEEE annex 31B and clause 30 Register-configurable loss-less flow control Auto Tx control pause packet generation and transmission based on Rx FIFO flags Rx XON/XOFF control pause packet recognition and stop Tx Layer, network management, and OAM Compliant with annex 4a and clause 30 Tx and Rx enable/disable Separate reset controls: MAC, FIFO, Avalon-MM Support all the relevant full-duplex 10-GbE DTE basic, mandatory, and recommended management capabilities and statistics Option: Statistics counters supporting RMON (RFC2819), Ethernet type MIB (RFC 3635), and interface group MIB (RFC 2863) Option: Local and line loop-back (inside RS) Single error injection in Tx Flexible clock domains Single core clock domain, or: Core + FIFO system side + Avalon-MM management bus Performance Full-duplex throughput rate of up to 10 Gbps in each direction Resource requirements 5050 LEs, 12 x M512, MAC + mgm’t registers + statistics + MDIO-MDC (no FIFO) The OAM stands for Operations, Administration and Maintenance here. Ethernet OAM is a layer 2 protocol that is used to monitor and remove network faults. Current worry is that the flow control implementation is not completed yet. Similarly the stat counter are not working with the exeption of good and bad packet counters. Loopback is not working either (and will not be for the first release for sure) The single error insertion is also not implemented and will not be in the first release.

10-GbE Reference Design Block Diagram
MAC only: XGMII MAC+PCS: pseudo-XGMII XAUI interface 10Gb Ethernet MAC 10GBase-X PCS + XAUI PMA Quad serial transceiver in GX devices Data Tx FIFO CTL and buffer MAC Tx CTL MAC XGMII Tx CTL Ctrl and Clk Non-promisc. Tx logic Internal system datapath interface, Avalon-ST To/from standard 10-GbE PHY device Data Rx FIFO CTL and buffer MAC Rx CTL MAC XGMII Rx CTL Ctrl and Clk Rx packet filter Standard module Optional module Statistics module Memory Mgmt. bus control and registers module Datapath Internal management bus, Avalon-MM Native mgmt. bus Control and clock External PHY device mgmt. module MDIO/MDC Mgmt. path

A 10-GbE Application Example Wireline: Switch/Router
x N x 2 Network line card Memory Switch fabric card Co-processor Memory Nx10GbE MAC Nx10GbE MAC . . Framer/ Ethernet MAC/ Mapper Classifier, traffic mgr., SPI-4 packet bridge Switch fabric interface Switch fabric External network interface NPU Line card control CPU Control logic and Ethernet MAC Ethernet PHY Ethernet switch Management interface Ethernet PHY 100M/1Gb MAC Memory System manager card x 2 x 2 Manager card control CPU Control logic and Ethernet MAC Ethernet PHY Datapath FPGA Management interface Ethernet PHY Control path Std. product Memory

Conclusion Stratix IV GX devices are industry’s first 40-nm transceiver-based FPGAs Altera offers best signal integrity features with data rate support up to 10 Gbps Protocol implementation is greatly simplified due to transceiver block features and hard IP

Designing with Transceiver-Based FPGAs at 40 nm

Similar presentations

Presentation on theme: "Designing with Transceiver-Based FPGAs at 40 nm"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

Designing with Transceiver-Based FPGAs at 40 nm

Similar presentations

Presentation on theme: "Designing with Transceiver-Based FPGAs at 40 nm"— Presentation transcript:

Similar presentations

About project

Feedback