1. CMS-GRPC status Imad Laktineh for the GRPC-CMS groups

2. Motivation Equip the stations RE1/1, RE2/1, RE3/1 and RE4/1 corresponding to high η region (1.6- 2.4) of the CMS with GRPC using new kind of semi-conductive glass. This allows to improve on trigger efficiency and physics performances.

3. Low-resistivity GRPC performance at high rate Detector R&D 9 kHz/cm 2 is highest rate one can get at DESY Single-Gap GRPC DESY, January 2012

4. Time Resolution < 40ps Beam Test@HZDR June, 2012 HV scanRate scan Detector R&D Multi-Gap GRPC

5. Electronics R&D CMS-GRPC Goals -To develop/adapt readout electronics which stands high rate and allows to exploit the time precision the RPC:  < 1 ns in case of single-gap GRPC  < 100 ps in case of multi-gap GRPC

6. R&D for single gap and sub-nanosecond time resolution - Use the 64-channel HARDROC ASICs used to read the GRPC pf the Semi Digital HCAL prototype of ILC - Use appropriate “Link Box” (available) - Use a TDC with better than 100 ps time - Design new PCB with pick-up strips (pitch of 1.5 mm) on two faces. The PCB is of a square shape (30X30 cm 2 ). ASICs are embedded on the PCB and only one side is read out. This can be used to equip the small GRPC already tested with the same electronics (but without the TDC ) and then use cosmic rays to check the sub-nanosecond time resolution. 4.7 mm 4.3mm Cabling is ongoing ASICs : HARDROC 64 channels, SiGe Trigger less mode 3 thresholds Range: 10 fC-15 pC Gain correction  uniformity I2C protocol.

7. R&D for multi gap and <100 ps time resolution -Use the 16-channel PETIROC ASICs (omega group-Paris) : High bandwidth preamp (GBWP> 10 GHz), <3 mW/ch, dual time and charge measurement up to 2500 pe, jitter < 10 ps rms To do list: - Develop a new Link Box - Use a TDC with 25 ps time resolution (available) per ASIC Design new PCB with pick-up strips (different values of pitch) ASICs and the Link Box are on the same PCB (on the edge) the two strip’s ends are read out with two different ASICs -The final size of the PCB will be that of RE1/X detector. The aim is to include a TDC in each channel (2014) OMEGA, NCEPU, TSINGUHA

8. 24Ch 25ps TDC module Cyclone-II FPGA EP2C35F484 C6 100M Ethernet Readout with TCP/IP support Socket for TCXO (opt.) Differential input connectorTsinghua university