1. “Advanced Process Integration” Instructor: Dr. W. Zagozdzon-Wosik
Class: ECE 7366
“Advanced Process Integration”
Instructor: Dr. W. Zagozdzon-Wosik

2. INTRODUCTION
• This course is about the requirements for silicon chip fabrication and the technologies used to meet to thee specific needs of MOS and bipolar devices for current and future generations of ICs. Integration of the current processes and new processes/materials for further scaled down devices will be covered.
• We will place a special emphasis on computer simulation tools to help understand these processes and as design tools.
• These simulation tools are more sophisticated in some technology areas than in others, but in all areas they have made tremendous progress in recent years.
• 1960 and 1990 integrated circuits.
• Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).
Increasing chip size - ≈ 16% per year.
“Creativity” in implementing functions.

3. Evolution of the Silicon Integrated Circuits since 1960s
Increasing: circuit complexity, packing density, chip size, speed, and reliability
Decreasing: feature size, price per bit, power (delay) product
1960s
1990s

4. G. Marcyk

5. Device Scaling Over Time
~13% decrease in feature size each year (now: ~10%)
Era of Simple Scaling
~16% increase in complexity each year (now:6.3% for µP, 12% for DRAM)
Cell dimensions
0.25µm in 1997
Scaling + Innovation
(ITRS)
Invention
Atomic dimensions
• The era of “easy” scaling is over. We are now in a period where
technology and device innovations are required. Beyond 2020, new
currently unknown inventions will be required.

7. 2004
2010
2013
2016
1997
1999
2001
2007
2 nodes
G. Marcyk, Intel

9. Trends in Scaling Si Microeletronics and MEMS

10. • Assumes that CMOS technology dominates over the entire roadmap.
Trends in Increasing Integration Scale of Circuits Past, Present, and Future ICs
ITRS at (2003 version update) – on class website.
• Assumes that CMOS technology dominates over the entire roadmap.
• 2 year cycle moving to 3 years (scaling + innovation now required).
• 1990 IBM demo of Å scale “lithography”.
• Technology appears to be capable of making structures much smaller than
currently known device limits.

11. Evolution of the Fabrication Process: The Planar Design of Bipolar Transistors
Beginning of the Silicon Technology and the End of Ge devices
Implementation of a masking oxide to protect junctions at the Si surface
Oxidation possible for Si not good for Ge
Lithography to open window in SiO2
Boron diffusion
SiO2
Mask
Phosphorus diffusion through the oxide mask
Oxidation and outdiffusion
The planar process of Hoerni and Fairchild (1950s)

12. Photolithography used for Pattern Formation
Beginning of Integrated Circuits in 1959
Kilby (TI) and Noyce (Fairchild Semiconductors)
Photolithography used for Pattern Formation
Sensitive to light
Durable in etching
• Basic lithography process
which is central to today’s
chip fabrication.

13. Alignment of Layers to Fabricate IC Elements
• Lithographic process allows integration of multiple devices side by side on a wafer.
Bipolar Transistor and resistors made in the base region
Accuracy of placement ~1/4 to 1/3 of the linewidth being printed
BJT B 0V
Vcc C E
Resistor
Base
R=L/W•Rs
Resistor
Emitter
Contact to collector
Collector

14. Schematic Cross-Section of Modern CMOS Integrated Circuit with Two Metal Levels
IC is located at the surface of a Si wafer (~500µm thick)
Interconnect M2
OXIDE
Via M1
Silicide
TiN
Oxide Isolation
PMOS
NMOS

15. Modern IC with a Five Level Metallization Scheme.
Planarization

16. Computer Simulation Tools (TCAD)
• Actual cross-section of a modern
microprocessor chip. Note the
multiple levels of metal and
planarization. (Intel website).
Computer Simulation Tools (TCAD)
•Most of the basic technologies in silicon chip manufacturing can now be simulated.
Simulation is now used for:
• Designing new processes and devices.
• Exploring the limits of semiconductor devices and technology (R&D).
• “Centering” manufacturing processes.
• Solving manufacturing problems (what-if?)

17. • Simulation of an
advanced local
oxidation process.
• Simulation of
photoresist exposure.

18. Semiconductor Devices
p-n Diodes
n+ for low resistance
Reverse biased diode
Forward biased diode
after Kano, Sem. Dev.

19. p-n Diodes at Thermal Equilibrium
At thermal equilibrium charge neutrality
qN+dxn=qN-Axp leads to asymmetrical depletion layers
Electric field only in the depletion layer
Uncompensated acceptors and donors

20. Breakdown of a p-n Diode
Zener effect
Avalanche effect
after Kano and Streetman

21. Breakdown Voltage of a p-n Diode
Eg 
5-7V
Ebr field increases with ND but not very much
Wdepl~1/√ND
Vbr=Ebr•Wdepl so Vbr decreases with ND
after Kano and Streetman

22. Transistors for digital and analg applications
MOSFET and Bipolar Junction Transistors

23. Bipolar Transistors VBE>0 VBC<0 a<1
E-B junction is forward biased=injects minority carriers to the base
Base (electrically neutral) is responsible for electron transport via diffusion (or drift also if the build in electric field exist) to collector
C-B diode is reverse biased and collects transported carries
VBE> VBC<0 IE IC IB
a<1
IE=IEn+IEp
IC=aIE
IB=IEp+Irec

24. Bipolar Junction Transistors
p-n-p
Individual device
n-p-n
Integrated circuit BJT

25. Bipolar Junction Transistors
Forwards bias
Reverse bias
minority carriers
Injected
electrons
Extracted
electrons
holes

26. Forward Operation Mode
Bipolar Junction Transistors
Early Effect
Forward Operation Mode
Early Voltage

27. Bipolar Junction Transistors
Breakdown Voltages
Common Emitter
Common Base
Collector-Base junction

28. Bipolar Junction Transistors
Current Gain b =a/1-a
b=IC/IB
Kirk Effect
Recombination in the E-B SCR
Gummel Plot

29. Bipolar Junction Transistors and a Switch
Schottky
Diode used in
n-p-n BJTs for
faster speed

30. MOS Field Effect Transistors (MOSFET)
NMOS and PMOS (used in CMOS circuits)
VG>VT to create strong inversion
Oxide
depletion

31. Operation of NMOS-FET Linear Region, Low VD
Saturation Region, Channel Starts to Pinch-Off
Saturation Region,
channel shortens beyond pinch-off, L’<L

32. Operation of MOS-FET ID(VD) Channel-Length-Modulation (Shorten by DL)
ID=kp[(VG-VT)VD-VD2/2
Device transconductance
kp=µnCoxW/L
larger for NMOS than PMOS
In CMOS for compensation use Wp>Wn

33. Scaled Down NMOS
DIBL
Proximity of the drain depletion layer charge sharing DIBL

34. Modern MOS Transistors
Gate
isolation
Source
Drain
LDD
LDD used to reduce the electric field
in the drain depletion region and
hot carrier effects
Self aligned contacts decrease the resistance

35. Semiconductor Technology Families
First circuits were based on BJT as a switch because MOS circuits limitations
related to large oxide charges
isolation BL
n-p-n

36. NMOS and CMOS Technologies
Enhancement NMOS Depletion NMOS
1970s
1980s and beyond
NMOS
PMOS
Smaller power consumption

37. Challenges For The Future Materials/process innovations
• Having a “roadmap” suggests that the future is well defined and there are
few challenges to making it happen.
• The truth is that there are enormous technical hurdles to actually achieving
the forecasts of the roadmap. Scaling is no longer enough.
• 3 stages for future development:
“Technology Performance Boosters”
Invention
Gate
• Spin-based devices
• Molecular devices
• Rapid single flux quantum
• Quantum cellular automata
• Resonant tunneling devices
• Single electron devices
Source
Drain
???
Materials/process innovations
NOW
Beyond Si CMOS
IN 15 YEARS??
Device innovations
IN 5-15 YEARS
Plummer et al.

38. Broader Impact of Silicon Technology
Tip on Stage
Individual Actuator
Part of 12 x 12 array
Cornell University
-0.75V
-2.5V
-2.25V
-2V
-1.75V
-1.5V
-1.25V
-1V
-0.5V
Source
Gate
Drain
SiO2
Stanford, Cornell
• Many other applications e.g. MEMs and many new device structures e.g. carbon
nanotube devices, all use basic silicon technology for fabrication.
Plummer et al.

39. Summary of Key Ideas
• ICs are widely regarded as one of the key components of the information age.
• Basic inventions between 1945 and 1970 laid the foundation for today's
silicon industry.
• For more than 40 years, "Moore's Law" (a doubling of chip complexity every
2-3 years) has held true.
• CMOS has become the dominant circuit technology because of its low DC
power consumption, high performance and flexible design options. Future
projections suggest these trends will continue at least 15 more years.
• Silicon technology has become a basic “toolset” for many areas of science and
engineering.
• Computer simulation tools have been widely used for device, circuit and system
design for many years. CAD tools are now being used for technology design.
• Chapter 1 also contains some review information on semiconductor materials
semiconductor devices. These topics will be useful in later chapters of the text.
Plummer et al.