1. TAP Controller for Cell-Based Design Myrna Bussiere, Project Leader Meagan Morrell

2. Purpose n To develop and implement a Test Access Port (TAP) Controller for use in the IEEE 1149.4 Boundary Scan tiny chip testing device n To understand Boundary Scan and to implement test sequences when chip has been fabricated

3. Topics of Discussion n TAP Controller overview n Initial design for digital logic n Layout of digital logic using Design Architect in Mentor Graphics n Simulation results from QuickSim in comparison to expected results n Layout of transistor level in IC Station

4. TAP Controller Overview n 16-State simple finite state machine n Three inputs n Nine outputs

5. Initial Design Process n Assigned 4-bit binary codes to each state of the TAP Controller n Produced a state table n Karnaugh maps were then derived n Simplified Boolean expressions were found n Digital logic design was formed

6. State Table Diagram

7. Digital Logic Design

8. Transistor Level of Gates

9. Transistor Level of D Flip-Flop

10. Simulation Results n Clock Frequency: 200ns n Low Power Consumption u Contains about 450 transistors u Total chip allows for 70,000 transistors

11. Simulation Results

12. Layout Design Process n Attempted to route manually to save space u Too time consuming, and many errors occurred n Used AutoRoute u Optimized space u Fast and no errors

13. IC Station Layout

14. Layered Layout

15. Detailed Layer Level

16. TAP Area Compared to Total Chip Area

17. Full Projected Layout of Tiny Chip

18. Summary n The TAP Controller for cell-based design has been successfully designed and laid out using the mentor graphics program n We have also tested it using two methods u It has passed both tests successfully and with no errors

19. Next Steps n Mach TA Simulation n Add one more ABM to full layout n Route all sub-components together in full layout n Submission to MOSIS for fabrication