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CoolRunner XPLA3 CPLD Overview - August 2000 File Number Here ®

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Presentation on theme: "CoolRunner XPLA3 CPLD Overview - August 2000 File Number Here ®"— Presentation transcript:

1 CoolRunner XPLA3 CPLD Overview - August 2000 File Number Here ®

2 ® www.xilinx.com Cr3lob 0800 - 2  Industry’s lowest power, highest performance CPLD —<100uA standby power at t PD =5ns —1/3 the total power of other CPLDs —Uses Fast Zero Power technology —1149.1 full JTAG compliance —Industrial temp grade operates from 2.7V  Ultra-small chip scale packaging —Perfect for portable applications  Robust architecture delivers great ISP —Full PLA and VFM for utilization and flexibility —Superior pin-locking —Fast input registers  WebPOWERED Software XPLA3 - The Lowest Power CPLD Solution

3 ® www.xilinx.com Cr3lob 0800 - 3 XPLA3 Shatters The Power Limits of Other CPLDs 10.0 CoolRunner Other CPLDs 1X 1000X 0.1 1.0 100.0 Icc Standby CoolRunner Other CPLDs Icc Total* * average versus comparable densities 1.0 0.5 Normalized mA

4 ® www.xilinx.com Cr3lob 0800 - 4  Longer lasting battery life —Longer system operation —Smaller battery packs —More functionality  Lower overall system cost —Smaller power supplies; fans & cooling requirements; sealed systems  Increased system reliability  Fits into hand-held size applications —Chip scale packaging provides optimum functionality in the smallest footprint  Enables products to become “field upgradable” —Accommodates last minute design changes via ISP XPLA3 Customer Value

5 ® www.xilinx.com Cr3lob 0800 - 5 Zero Power Interconnect Array Logic Block I/O 15 I/O Logic (Mcells) PLA Logic I/O 0 I/O 1 I/O 2 I/O 15 I/O Logic (Mcells) PLA Logic I/O 0 I/O 1 I/O 2 3.3v ISP Architecture  ZIA - virtual crosspoint switch  16 macrocells per logic block  Full PLA for best connectivity  36 inputs to each logic block

6 ® www.xilinx.com Cr3lob 0800 - 6 PLA Benefit Maximum Flexibility  Industry’s first and most efficient PLD architecture  Shared common logic —Allows higher density logic packing  Any and all product terms can be shared by any macrocell —No stranded product terms  Wide logic runs at full speed —Continued deterministic timing with additional product terms

7 ® www.xilinx.com Cr3lob 0800 - 7 Low Power, No Effort  Competitive CPLDs use sense amp product terms —Always consumes power-- even at standby —Performance is traded for power consumption as devices get larger  CoolRunner FZP design uses TotalCMOS product terms —Virtually no standby current —Total currents @ 1/3 the competition —Combines high performance and low power —No power limits on device size Sense Amplifier.25mA each - Standby Higher ICC at Fmax FZP: CMOS Everywhere - Zero Static Power

8 ® www.xilinx.com Cr3lob 0800 - 8 Head to Head Results 0 20 40 60 80 100 120 140 160 015102050100150 128 Macrocell Power Comparison XCR3128XL vs Vendor A Vendor A (Turbo) Zero standby current (22 uA) Faster in low power applications Lower power in fast applications Vendor A (Non-Turbo) XCR3128XL Required Current (mA) Frequency (MHz.)

9 ® www.xilinx.com Cr3lob 0800 - 9 Lower Power = Higher System Reliability  Activation Energy E A Aggravated by Temperature!  Increased Temperature = Decreased Reliability FITS Time Infant Mortality Constant Failure Wearout Temperature

10 ® www.xilinx.com Cr3lob 0800 - 10 Lower Power = Lower Heat Dissipation  Eliminates Expensive Heat Sinks & Fans —Heat Sinks: $ 0.50 - $ 12.00 —Fans:$ 3.50 and up  Decrease Power supply component size  Necessary for: —High Performance —Small Portable Form Factors –Computing Lap & Palm Enclosures –Higher product density Less Heat = Higher Performance & Cost Savings & Reliability!

11 ® www.xilinx.com Cr3lob 0800 - 11 Lower Power = Lower Thermal Emissions θ JA = Junction-to-Ambient Thermal Resistance Die Package T J = Junction (Die) Temperature T C = Case Temperature θ JC = Junction-to-Case Thermal Resistance T A = Ambient or Still Air Temperature Board T C = (P d X θ JA ) + T A

12 ® www.xilinx.com Cr3lob 0800 - 12 Thermal Emissions Comparison  Devices programmed with 16 bit counters with the MSB brought out to an LED and operated at 50MHz  Where applicable, competitive devices were in non-turbo mode  Note the MACH4 device is 128 macrocells (no availability), and the Lattice part is 192 macrocells (largest in the family) 2530354045505560 Degrees Centigrade Ambient Xilinx XCR3256XL-7TC144 Cypress CY37256VP160-100AC Lattice M4LV-128/64-10YC Altera EPM7256AETC144-7 Altera EPM3256ATC144-7 Lattice ispLSI2192VE-100LT128

13 ® www.xilinx.com Cr3lob 0800 - 13 Lower Power = Smaller Packages  XPLA3 supports small industry standard packages  New Chip Scale Packaging —CS48 —CP56 6x6mm, 0.5mm pitch 7x7mm, 0.8mm pitch 16x16mm, 1.27 pitch 44 PLCC CS48 CP56

14 ® www.xilinx.com Cr3lob 0800 - 14 Lower Power = Smaller Packages  56-Ball 0.5mm CSP  Provides 44 I/O’s —0.5mm pitch  36 mm 2 footprint  Ideal for handheld & portable applications —PDAs —Portable PCs —Cellular Phones —Telecom & Networking Equipment —Network Appliances

15 ® www.xilinx.com Cr3lob 0800 - 15 CoolRunner Delivers Lowest Power @ Any Speed  Reduce Icc requirements while increasing system reliability —Smaller power supply —Eliminate fans —Smaller equipment  Smaller device packaging —Less board area & more logic packing density Competitive CPLDs @ 0 MHz CoolRunner... System Speed For Free!! Frequency Idd

16 ® www.xilinx.com Cr3lob 0800 - 16 CoolRunner XPLA3 Family 3264 800 1600 56 Packages (Max. User I/Os) 44VQ (36) 44PC (36) 48CS (36) 44VQ (36) 44PC (36) 48CS (40) 56CP (48) 100VQ (68) 128 320 0 100VQ (84) 144CS (108) 144TQ (108) 133 (166*) XCR3032X L XCR3064XLXCR3128XLXCR3256XL Macrocells Usable Gates t PD (ns) f SYS (MHz) 256 6400 133 166 200 144TQ (120) 208PQ (164) 280CS (164) 7.5 7.5 (6*) XCR3384XL 384 9600 7.5 133 208PQ (164) 256FG (tbd) 280CS(220) *Available 12/00

17 ® www.xilinx.com Cr3lob 0800 - 17 XPLA3 - Sets New Standard in CPLDs  Industry’s lowest power CPLD  Provides real benefits to portable, handheld markets  Free WebPOWERED software solution  Expands Xilinx suite of “high volume” programmable solutions

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