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ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE.

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Presentation on theme: "ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE."— Presentation transcript:

1 ELEC 7770: Advanced VLSI Design (Agrawal)1 ELEC 7770 Advanced VLSI Design Spring 2014 Power and Ground Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr14 Spring 2014, Mar 21...

2 References  Q. K. Zhu, Power Distribution Network Design for VLSI, Hoboken, New Jersey: Wiley, 2004.  M. Popovich, A. Mezhiba and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer, 2008.  C.-K. Koh, J. Jain and S. F. Cauley, “Synthesis of Clock and Power/Ground Network,” Chapter 13, L.-T. Wang, Y.-W. Chang and K.-T. Cheng (Editors), Electronic Design Automation, Morgan- Kaufmann, 2009. pp. 751-850.  J. Fu, Z. Luo, X. Hong, Y. Cai, S. X.-D. Tan, Z. Pan, “VLSI On-Chip Power/Ground Network Optimization Considering Decap Leakage Currents,” Proc. Asia and South Pacific Design Automation Conf., 2005, pp. 735-738.  Decoupling Capacitors, http://www.vlsichipdesign.com/index.php/Chip-Design- Articles/decoupling-capacitors.html http://www.vlsichipdesign.com/index.php/Chip-Design- Articles/decoupling-capacitors.html http://www.vlsichipdesign.com/index.php/Chip-Design- Articles/decoupling-capacitors.html ELEC 7770: Advanced VLSI Design (Agrawal)2Spring 2014, Mar 21...

3 Supply Voltage ELEC 7770: Advanced VLSI Design (Agrawal)3 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.25 0.18 0.13 0.1 Minimum feature size (μm) Supply voltage (V) Spring 2014, Mar 21...

4 Gate Oxide Thickness ELEC 7770: Advanced VLSI Design (Agrawal)4 60 50 40 30 20 10 0 0.25 0.18 0.13 0.1 Minimum feature size (μm) Gate oxide thickness (A) High gate leakage Spring 2014, Mar 21...

5 Power Supply Noise  Transient behavior of supply voltage and ground level.  Caused by transient currents:  Power droop  Ground bounce ELEC 7770: Advanced VLSI Design (Agrawal)5Spring 2014, Mar 21...

6 Power Supply ELEC 7770: Advanced VLSI Design (Agrawal)6 +–+– Gate 1 Gate 2 VDD Rg RCRC RCRC V(t) Spring 2014, Mar 21...

7 Switching Transients  Only Gate 1 switches (turns on): V(t) = VDD – Rg VDD exp[– t/{C(R+Rg)}]/(R+Rg) ELEC 7770: Advanced VLSI Design (Agrawal)7 V(t) VDD 0time, t VDD Rg/(R+Rg) Spring 2014, Mar 21...

8 Multiple Gates Switching ELEC 7770: Advanced VLSI Design (Agrawal)8 Gate output voltage VDD 0time, t many Number of gates switching 1 2 3 Spring 2014, Mar 21...

9 Decoupling Capacitor  A capacitor to isolate two electrical circuits.  Illustration: An approximate model: ELEC 7770: Advanced VLSI Design (Agrawal)9 +–+– VDD = 1 Rg Rd Cd IL VL(t) t i(t) a t=0 Spring 2014, Mar 21...

10 Approximate Load Current, IL 0,t < 0 at,t < tp IL= a(2tp – t),t < 2tp 0,t > 2tp ELEC 7770: Advanced VLSI Design (Agrawal)10Spring 2014, Mar 21...

11 Transient Load Voltage VL(t) = 1 – a Rg [ t – Cd Rg (1 – e – t/T ) ], 0 < t < tp T=Cd (Rg + Rd) ELEC 7770: Advanced VLSI Design (Agrawal)11Spring 2014, Mar 21...

12 Realizing Decoupling Capacitor ELEC 7770: Advanced VLSI Design (Agrawal)12 GND SB D VDD GND SB D VDD OR Spring 2014, Mar 21...

13 Capacitance Cd=γ×WL×ε×ε 0 /Tox ≈0.26fF, for 70nm BSIM L=38nm,W=200nm γ=1.5462 ε=4 ELEC 7770: Advanced VLSI Design (Agrawal)13Spring 2014, Mar 21...

14 Leakage Resistance Igate=α × e – βTox ×W where α and β are technology parameters. Rd=VL(t)/Igate Because V(t) is a function of time, Rd is difficult to estimate. The decoupling capacitance is simulated in spice. ELEC 7770: Advanced VLSI Design (Agrawal)14Spring 2014, Mar 21...

15 Power-Ground Layout ELEC 7770: Advanced VLSI Design (Agrawal)15 Vss Vdd Vss Vdd Solder bump pads M5 M4 Via Vdd/Vss supply Vdd/Vss equalization Spring 2014, Mar 21...

16 Power Grid ELEC 7770: Advanced VLSI Design (Agrawal)16 +–+– Spring 2014, Mar 21...

17 Nodal Analysis ELEC 7770: Advanced VLSI Design (Agrawal)17 V1 V2 V3 V4 Ci Vi Bi Apply KCL to node i: 4 ∑ (Vk – Vi) gk – Ci ∂Vi/∂t = Bi k=1 g1 g2 g3 g4 Spring 2014, Mar 21...

18 Nodal Analysis ELEC 7770: Advanced VLSI Design (Agrawal)18 G V – C V’ = B WhereG is conductance matrix V is nodal voltage vector C is admittance matrix B is vector of currents V(t) is a function of time, V(0) = VDD B(t) is a function of time, B(0) ≈ 0 or leakage current Spring 2014, Mar 21...

19 Wire Width Considerations  Increase wire width to reduce resistance:  Control voltage drop for given current  Reduce resistive loss  Reduce wire width to reduce wiring area.  Minimum width restricted to avoid metal migration (reliability consideration). ELEC 7770: Advanced VLSI Design (Agrawal)19Spring 2014, Mar 21...

20 A Minimization Problem ELEC 7770: Advanced VLSI Design (Agrawal)20 Minimize total metal area: n A= ∑ w i s i =∑ | ρ C i s i 2 | / x ii=1 Where n=number of branches in power network w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch Subject to several conditions. Spring 2014, Mar 21...

21 Condition 1: Voltage Drop ELEC 7770: Advanced VLSI Design (Agrawal)21 Voltage drop on path P k : ∑ x i ≤Δv k i ε P k Where Δv k =maximum allowable voltage drop on kth path Spring 2014, Mar 21...

22 Condition 2: Minimum Width ELEC 7770: Advanced VLSI Design (Agrawal)22 Minimum width allowed by fabrication process: w i =ρ C i s i / x i ≥W Where w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch W=minimum line width Spring 2014, Mar 21...

23 Condition 3: Metal Migration ELEC 7770: Advanced VLSI Design (Agrawal)23 Do not exceed maximum current to wire-width ratio: C i / w i = x i /(ρ s i )≤σ i Where w i =metal width of ith branch s i =length of ith branch ρ=metal resistivity C i =maximum current in ith branch x i =voltage drop in ith branch σ i =maximum allowable current density across ith branch Spring 2014, Mar 21...

24 Decoupling Capacitance ELEC 7770: Advanced VLSI Design (Agrawal)24 +–+– VDD Rg Cd I(t) Spring 2014, Mar 21...

25 Decoupling Capacitance  Initial charge on Cd, Q 0 = Cd VDD  I(t): current waveform at a node  T: duration of current  Total charge supplied to load: T Q = ∫ I(t) dt 0 ELEC 7770: Advanced VLSI Design (Agrawal)25Spring 2014, Mar 21...

26 Decoupling Capacitance  Assume that charge is completely supplied by Cd.  Remaining charge on Cd = Cd VDD – Q  Voltage of supply node = VDD – Q/Cd  For a maximum supply noise ΔVDDmax, VDD – (VDD – Q/Cd) ≤ ΔVDDmax OrCd≥Q / ΔVDDmax ELEC 7770: Advanced VLSI Design (Agrawal)26Spring 2014, Mar 21...

27 A High-Voltage On-Chip Power Distribution Network June 28, 2013 Master’s Thesis www.eng.auburn.edu/~vagrawal/THESIS/SHIHAB/Mustafa_Thesis.pdf Mustafa M. Shihab Auburn University ECE Department June 2013 ELEC 7770: Advanced VLSI Design (Agrawal)27Spring 2014, Mar 21...

28 On-Chip Power Distribution Network  Power Distribution ‘Grid’: Source: N. Weste et al., CMOS VLSI design: A Circuits and Systems ELEC 7770: Advanced VLSI Design (Agrawal)28Spring 2014, Mar 21...

29 I 2 R Power Loss 29 Take Away: For a 100 mile long line carrying 1000 MW of energy @ 138 kV power loss = 26.25% @ 345 kV power loss = 4.2% @ 765 kV power loss = 1.1% to 0.5% Source: “American Electric Power Transmission Facts “, http://bit.ly/11nUMvf ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

30 I 2 R Power Loss on a Chip 30  I 2 R Loss in On-Chip Power Distribution Network: Increasing Current Density Increasing Wire Resistivity Increasing I 2 R Loss Technology Scaling ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

31 Problem Statement Propose a scheme for delivering power to different parts of a large integrated circuit, such as cores on a system-on-chip (SoC), at a higher than the regular (V DD ) voltage. The increase in voltage will lower the current on the grid, and thereby reduces the I 2 R loss in the on-chip power distribution network. 31 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

32 Typical Power Distribution Network 32 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

33 Proposed Power Distribution Network 33 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

34 Present Distribution Scheme 34  Example: Low-Voltage (V DD ) Power Grid with 9 loads ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

35 Proposed Distribution Scheme 35  Example: High-Voltage (3V) Power Grid with 9 loads ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

36 Result: Low Voltage Distribution 36 Number of Loads Load Power (W) Grid Power (W) Total Power (W) Efficiency (%) 110.131.1388.50 440.674.6785.65 991.6910.6984.19 16 3.5719.5781.76 25 7.0232.0278.08 64 23.7687.7672.93 100 49.32149.3266.97 256 169.4425.460.18 Supply Voltage: 1V, Load: 1W Grid Resistances: 0.5 Ω (ITRS 2012) ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

37 Low Voltage PDN Power Transfer 37 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

38 Low Voltage PDN Efficiency 38 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

39 Result: High Voltage Distribution 39 Number of Loads Load Power (W) Grid Power (W) Total Power (W) H-V PDN Efficiency (%) 110.011.0198.58 440.074.0798.17 990.199.1997.96 16 0.4016.4097.58 25 0.7825.7896.97 64 2.6466.6496.04 100 5.48105.4894.80 256 18.82274.8293.15 Supply Voltage: 3 V, Load: 1W Grid Resistances: 0.5 Ω (ITRS 2012) DC-DC Converter: LTC 3411-A Linear Technology, 100% Efficiency ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

40 High Voltage PDN Power Transfer 40 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

41 High Voltage PDN Efficiency 41 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

42 Result: High Voltage Distribution Number of Loads Load Power (W) Grid Power (W) Total Power (W)Efficiency (%) 110.021.0298.04 440.114.1197.32 990.399.3995.85 16 1.2117.2192.97 25 2.6827.6890.32 64 9.1273.1287.53 100 18.97118.9784.05 256 63.3319.380.18 Supply Voltage: 3 V, Load: 1W Grid Resistances: 0.5 Ω (ITRS 2012) DC-DC Converter: LTC 3411-A Linear Technology, 80% Efficiency ELEC 7770: Advanced VLSI Design (Agrawal)42Spring 2014, Mar 21...

43 High Voltage PDN Power Transfer 43 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

44 High Voltage PDN Efficiency 44 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

45 Comparing Grid Power Loss 45 Number of Loads Load Power (W) PDN Grid Power Loss (W) Low- Voltage PDN High-Voltage (100% Eff. Converter) High-Voltage (80% Eff. Converter) 11 0.130.01 0.02 44 0.670.07 0.11 99 1.690.19 0.39 16 3.570.40 1.21 25 7.020.78 2.68 64 23.762.64 9.12 100 49.325.48 18.97 256 169.4018.82 63.3 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

46 Comparing Grid Power Loss 46 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

47 Comparing PDN Efficiencies 47 Number of Loads Grid Efficiency (%) Low-Voltage PDN High-Voltage PDN (100% Eff. Converter) High-Voltage PDN (80% Eff. Converter) 1 88.5098.5898.04 4 85.6598.1797.32 9 84.1997.9695.85 16 81.7697.5892.97 25 78.0896.9790.32 64 72.9396.0487.53 100 66.9794.8084.05 256 60.1893.1580.18 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

48 Comparing PDN Efficiencies 48 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

49 Challenges  DC-DC Converter Design:  Efficiency  Power  Area  Output Drive Capacity  Fabrication 49 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

50 Reported Developments  Input Voltage: 3.3 V Output Voltage: 1.3 V – 1.6 V Output Voltage: 1.3 V – 1.6 V Output Drive Current: 26 mA Output Drive Current: 26 mA Efficiency: 75% - 87% Efficiency: 75% - 87%  Input Voltage: 3.6 V & 5.4 V Output Voltage: 0.9 V Output Voltage: 0.9 V Output Drive Current: 250 mA Output Drive Current: 250 mA Efficiency: 87.8% & 79.6% Efficiency: 87.8% & 79.6% 50 Sources: B. Maity et al., Journal of Low Power Electronics 2012 V. Kursun et al., Multi-voltage CMOS Circuit Design. Wiley, 2006 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

51  Have the capability of driving output loads of reasonable size  Have power efficiency of 90% or higher  Meet the tight area requirements of modern high-density ICs  Be fabricated on chip as a part of the SoC  Have ‘regulator’ capability to convert a range of input voltage to the designated output voltage 51 Future Work DC-DC Converters ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

52 References  D. Chinnery and K. Keutzer, Closing the Power Gap Between ASIC and Custom: Tools and Techniques for Low Power Design. Springer, 2007.  M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design. Springer, 2007.  V. Kursun and E. Friedman, Multivoltage CMOS Circuit Design. Wiley, 2006.  C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation Over Different Technology Generations," Proc. International Symp. Low Power Electronics and Design, 2003, pp. 116-121.  B. C. Paul, A. Agarwal, and K. Roy, "Low-Power Design Techniques for Scaled Technologies,“ Integration, the VLSI Journal, vol. 39, no. 2, pp. 64-89, 2006.  "Linear Technology: LT3411A DC-DC Converter Demo Circuit @ONLINE,“ Nov. 2011.  M. Pedram and J. M. Rabaey, Power Aware Design Methodologies. Springer, 2002.  M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, “On-Chip Power Distribution Grids with Multiple Supply Voltages for High-Performance Integrated Circuits," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 16, no. 7, pp. 908-921, 2008.  Q. K. Zhu, Power Distribution Network Design for VLSI. Wiley-Interscience, 2004. 52 ELEC 7770: Advanced VLSI Design (Agrawal)Spring 2014, Mar 21...

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