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Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 32: November 28, 2011 Inductive Noise
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Today Inductive Responses Calculating L Where do inductances show up Impact of inductance on digital circuits How address Penn ESE370 Fall2011 -- DeHon 2
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Response What happens here? Penn ESE370 Fall2011 -- DeHon 3
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LC Response Penn ESE370 Fall2011 -- DeHon 4 V2V2
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LC Response Penn ESE370 Fall2011 -- DeHon 5
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LC Response Penn ESE370 Fall2011 -- DeHon 6
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LC Response Penn ESE370 Fall2011 -- DeHon 7
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LC Response Penn ESE370 Fall2011 -- DeHon 8
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LC Response Penn ESE370 Fall2011 -- DeHon 9
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LC Response Penn ESE370 Fall2011 -- DeHon 10
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LC Response Penn ESE370 Fall2011 -- DeHon 11
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Response? Penn ESE370 Fall2011 -- DeHon 12
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RLC Response Penn ESE370 Fall2011 -- DeHon 13 V2V2
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RLC Response Penn ESE370 Fall2011 -- DeHon 14
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RLC Response Penn ESE370 Fall2011 -- DeHon 15
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Solving for w Penn ESE370 Fall2011 -- DeHon 16
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RLC Penn ESE370 Fall2011 -- DeHon 17
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RLC Penn ESE370 Fall2011 -- DeHon 18
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RLC For Oscillation Decay Penn ESE370 Fall2011 -- DeHon 19
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RLC Response (R=100) Penn ESE370 Fall2011 -- DeHon 20
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When Oscillate Penn ESE370 Fall2011 -- DeHon 21
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RLC Response Penn ESE370 Fall2011 -- DeHon 22
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Inductance of Wire Penn ESE370 Fall2011 -- DeHon 23
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Inductance: Wire over Ground Plane Inductance per cm with h=3mil, w=5mil? Penn ESE370 Fall2011 -- DeHon 24
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Lwire Penn ESE370 Fall2011 -- DeHon 25 C and L per unit length
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Chip Inductance C wire = 0.16 pF for the 1mm) C wire = 0.16nF/m Permeability 0 ≈ Si02 =12.6×10 -7 H/m Permitivity ox =3.5×10 -11 F/m Penn ESE370 Fall2011 -- DeHon 26
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On Chip C wire = 0.16 pF for the 1mm) C wire = 0.16nF/m Permeability 0 ≈ Si02 =12.6×10 -7 H/m Permitivity ox =3.5×10 -11 F/m pH (for 1 mm) Penn ESE370 Fall2011 -- DeHon 27
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Comparisons 5mil trace on PCB Protoboard wires (0.6mm diameter) –About 7nH/cm –http://www.consultrsr.com/resources/eis/induct5.htm On chip wire –0.28nH/mm = 2.8nH/cm Penn ESE370 Fall2011 -- DeHon 28
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Inductors Bond pads Chip leads Long wire runs Cables Penn ESE370 Fall2011 -- DeHon 29 Src: http://en.wikipedia.org/wiki/File:Wirebonding2.svg
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Where Arise Penn ESE370 Fall2011 -- DeHon 30
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Signal Path Penn ESE370 Fall2011 -- DeHon 31
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Power Ground Penn ESE370 Fall2011 -- DeHon 32
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Shared Power/Ground Example: 74x04 Penn ESE370 Fall2011 -- DeHon 33
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Estimate R eq, C eq for gates in parallel –R 0 = 25K –C 0 = 0.01 fF say 10C 0 =0.1fF for typical load 250 gates switching at clock R eq = 100 C eq =25fF Assume L=1nH Penn ESE370 Fall2011 -- DeHon 34
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Power Ground Penn ESE370 Fall2011 -- DeHon 35
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RLC Response Penn ESE370 Fall2011 -- DeHon 36
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Today’s Chips How many gates? Penn ESE370 Fall2011 -- DeHon 37
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Multiple Power/Ground Pins Use many power/ground pins How many pins on a package? Divide switching gates by pins –To get effective load on each pin Penn ESE370 Fall2011 -- DeHon 38
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How Improve Penn ESE370 Fall2011 -- DeHon 39
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Minimize the L Make wires short Use power and ground planes Penn ESE370 Fall2011 -- DeHon 40
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Add Good C’s Bypass Capacitors – inside the inductances –On board –On package –On chip Penn ESE370 Fall2011 -- DeHon 41
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Bypass Capacitor Example Penn ESE370 Fall2011 -- DeHon 42
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Bypassed Supplies (@ transistor) Penn ESE370 Fall2011 -- DeHon 43
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Bypassed Output Penn ESE370 Fall2011 -- DeHon 44
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Minimize Current Draw More Power/Ground Pins Slower rise/fall times Spread out switching Penn ESE370 Fall2011 -- DeHon 45
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Admin HW6 out Project 3 out Wednesday Lecture Friday in Lab –Lab instructions out Wednesday Penn ESE370 Fall2011 -- DeHon 46
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Idea Long wires are inductive –Avoid them –Especially on power supplies Bypass capacitors help Penn ESE370 Fall2011 -- DeHon 47
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