1. STICK DIAGRAM EMT251

2. Schematic vs Layout In Out V DD GND Inverter circuit

3. Schematic vs Layout A Out V DD GND B 2-input NAND gate

4. Stick Diagram A stick diagram is a graphical view of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

5. Stick Diagram Represents relative positions of transistors Stick diagrams help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers In Out V DD GND Inverter A Out V DD GND B NAND2

6. Stick Diagram Metal (BLUE) Polysilicion (RED) N-Diffusion (Green) P-Diffusion (Brown) Contact / Via Layers

7. How to design? C AB X = C (A + B) B A C i j j V DD X X i GND AB C PUN PDN A B C Logic Graph / Euler Path

8. Stick Diagram of C (A + B) X CABABC X V DD GND V DD GND

9. Consistent Euler Path j V DD X X i GND AB C ABC

10. Example C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D

11. LAYOUT DESIGN RULES EMT251

12. 3D View

13. Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

14. CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

15. Draw NMOS: 1.Active + Poly 2.Contact_to_active 3.Metal1 above Contact 4.N-Plus Select 5.P-Well 6.P-Well Contact Draw PMOS: 1.Active + Poly 2.Contact_to_active 3.Metal1 above Contact 4.P-Plus Select 5.N-Well 6.N-Well Contact

16. Layers in 0.35  m CMOS process

17. Intra-Layer Design Rules Metal2 4 3

18. Transistor Layout

19. Vias and Contacts

20. Select Layer

21. CMOS Inverter Layout In Out GND V DD (a) Layout