1. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Project Plan 2003 FED Project aiming to satisfy 2 demands/timescales: Module Tester FEDs: “July ‘03 (2) / end ‘03 (2) / beg ‘04 (2) / mid ‘04 (6)” 96 Opto for large scale silicon tracker modules (can’t use FED-PMCs.) need to provide restricted FED functionality assumes we can use FEDv1 pcbs Pre-Production Manufacture: Q1-2/04 to stay on final CMS installation schedule need to demonstrate full functionality assumes new iteration FEDv2 pcbs

2. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 CMS Tracker FED Schedule FED x 450 installation at CERN expected to start Q3 2005 DesignTest Production & Installation Pre-Pro FEDv3 (500)FEDv2 (20)FEDv1 (20) ST, IC, JC -------------------------------------> EF ------------>

3. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Module Testers Requirements July ‘03 “To Readout Virgin Raw Data formatted as DAQ events via VME in response to TTC trigger and clock.” Trigger & Readout rates are not critical. Functionality Does require: Scope Mode and Software Triggers for set up. Controls from VME for run mode, clock source, clock skew, OptoRx offsets, Counters for triggers & errors VME accessible Event buffer occupancy & lengths for readout. System ACE loading, Resets on TTC Chan A, Hardware throttle output. FED delivered as a Package including Software to drive the Firmware. Does not require: S-LINK readout, Clustering mode, Spy Channel, TTC chan B, TCS (but maybe simple throttle), DAC control, pedestal/threshold data, System ACE interface, VME64x config EPROM…, VME Interrupts, Temp chip control…

4. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FEDv1 Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Modularity 9U VME64x Form Factor Modularity matches Opto Links 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-End module / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

5. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Pre-Production FEDv2 Does require: S-LINK readout, Clustering mode, Spy Channel, TTC chan B, TCS (but maybe simple throttle), DAC control, pedestal/threshold data, System ACE control and in situ- programming, VME64x config EPROM…, VME Interrupts, Temp chip control… All operating at target Trigger Rate of 100 kHz! Have to demonstrate full functionality before next iteration FEDv2. Collaborative project with Imperial. We share testing. But they also wish to contribute some Firmware design in addition to Software design. NB Strong pressure from customer to only make those changes on FEDv2 which are absolutely necessary. although we must also consider final manufacturing costs.

6. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Testing so far End of Q1. Already achieved in Testing: Boards passed JTAG. Basic FE Analogue tests (with Cross-Point card.) Analogue capture with Chip Scope. FPGA configuration from System ACE. Tested DDR from Delay to FE FPGA. Basic external VME interface (with Block Transfer.) First Opto signal tests. Further tests at Imperial. Experience is positive so far. Tests are progressing well. Found a few “patches” needed on the board. So far no “show stoppers” for Module Testers with FEDv1 design. Nevertheless customer considers us to be about 3-6 months behind schedule. Still Ok providing we can use FEDv1 pcb for Module Testers. Now need to provide estimates of time needed to implement remaining Firmware.

7. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Firmware Status: Ready to start trying Final Designs on FED together with test firmware. Delay FPGA: Final version synthesised and under test. FE FPGA: Final version synthesised and “ready” for test. BE FPGA: Data path up to QDR filling synthesised and ready for test. TTC chan A interface implemented. Read path to VME in progress incl DAQ formatting. VME FPGA: External VME cycles tested. Serial comms to BE close to test. To do... parallel link to BE incl. readout interface. Steps towards providing Module Test functionality...

8. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Firmware Milestone Tests in Q2/03 Load Final Delay design. Test DDR to FE FPGA. (ChipScope in FE) Control and read-back via VME to FE FPGAs (e.g. OptoRx ctrl). Implement serial comms from VME to BE* first and then on to FE. VME end nearly ready. BE take receiver block from FE design. Provide simple register map and test with software. (Later extend to other controls eg to test clock skewing.) NB Uses Final design of FE, Delay and VME. Test design in BE. Test Final FE design with Software trigger (no handshakes.) Test design in BE with ChipScope. Meanwhile Test Final BE design writing to QDR. Use test data generator load in FE’s 1->8 (is existing code synthesisable?). Or do test with Final FE design. Test with Software trigger=FE Scope Mode. Extend Final BE to test QDR readout to VME (using test generators or Scope mode in FE). Test parallel link from BE to VME and readout protocol. Readout via CPU. Divide and Conquer … in 3 months...

9. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Firmware Milestone Tests in Q2/03 Test Final FE Virgin Raw data mode (header finding.) Need APV frame generator (OptoTest Card?) Add synch clock and trigger inputs (backplane?). Need clock and trigger select logic. Use TTC to provide ext clock and trigger. Mostly implemented. But need TTC VME cards to do this test (Imperial?) Need clock and trigger select logic. Add Event/Header formatting for readout. Test with Final FE design. Readout interface Parallel Link BE to VME, with register for event length and nr events pending. In BE read by VME. Software triggers. Simply a register to generate a Scope Trigger. Control registers & Counters for nr triggers, (resets), errors…. In BE read by VME.

10. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FEDv1 Overview VME-FPGA TTCrx BE-FPGA Event Builder Buffers FPGA Configuration Compact Flash Power DC-DC DAQ Interface 12 Front-End Modules x 8 Double-sided board CERN Opto- Rx Analogue/Digital 96 Tracker Opto Fibres VME Interface Xilinx Virtex-II FPGA Modularity 9U VME64x Form Factor Modularity matches Opto Links 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-End module / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration FE-FPGA Cluster Finder TTC TCS Temp Monitor JTAG TCS : Trigger Control System 9U VME64x

11. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Registers Software: Up to now only peek & poke program to VME from Linux. Module Testers need to integrate FED software into their (complicated) system. Need FED Application Programming Interface. A list of software functions FED responds to. Need register map/list. Serial string commands to load and read back FE/Delay registers as described by Bill. Extra serial string commands (same mechanism) to load and read back following registers in BE: Register to reset BE status/counters Register to read BE status, eg FIFO status Register to select TTC clock or test clock. TTC internal registers access Register to select test clock. Register to select TTC trigger or test source. Register to enable triggers (e.g. whilst loading FE FPGAs.) Register to send a software trigger (=Scope mode/Frame sync to FE FPGA).

12. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Registers Registers to count nr triggers received (and resets and errors?) Register to select BE readout mode VME or S-LINK Register to read nr of events pending to readout (polled by CPU) Register to read length of current event to readout (gives nr of words to readout event). And a few local in VME e.g. FED ID, Test memory to detect board, Enable FED register

13. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FEDv1 Event Readout Protocol DAQ Trailer Formatted FED Data DAQ Header Tracker Header Readout (via VME) Formatted Events identical? to those sent to S-LINK Load Parameters e.g. Peds, Clock skews Set run mode Select clock and trigger source Start Run and enable Triggers/Frames Poll on Event Occupancy Counter Get length of event Readout that event (in chunks) done (BE decrements Event Occupancy Counter after last byte sent to VME?) Repeat until Run stop Periodically check local status registers and counters Event Formats: Virgin Raw Data. Raw APV frames. *Scope Mode or Software Trigger Both are fixed event sizes within a Run. (*Empty Tracker Header.)

14. Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Test Equipment Cross-Point cards for electrical inputs. Most useful in Scope modes. Second Opto Test card (after Easter). Most convenient for APV patterns. Needed for Raw Data (header finding) readout tests with FE FPGA. Have TTC VME cards in hand. New PC/VME Interface (SBS optical link card) after Easter. Standard LHC VME64x Crate in May?