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© 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM RTL-Synchronized Transaction Reference Models Dave Whipp Fast-Chip Inc.

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Presentation on theme: "© 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM RTL-Synchronized Transaction Reference Models Dave Whipp Fast-Chip Inc."— Presentation transcript:

1 © 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM RTL-Synchronized Transaction Reference Models Dave Whipp Fast-Chip Inc.

2 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Motivation ›Needed Cycle Verification Now, not 6 months later ›Why build two models, when one will do We had a working “functional” model ›Don’t Chase RTL Avoid modeling artifacts of the implementation

3 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Overview 1.What is Transaction Synchronization 2.Patterns in Transaction Synchronization 3.Methodology, Futures, Summary

4 © 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM Part 1 What is Transaction Synchronization?

5 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM A Functional Model int classify_packet ( Packet packet_data, Uint32 rule_address ) { int result = ITERATE while (result == ITERATE) { RuleStruct rule; read_rule(&rule, rule_address); int field = extract(rule, packet_data); interpret(rule, field, &result, &rule_address); } return result; }

6 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM “Bringup” Flow test.script C-sim RTL-sim Compare csim.log rtl.log

7 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Transaction Interactions Read-Rule Rules DB Write-Rule Thread AThread B

8 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Trace Files ›A trace of the sequence of transaction steps ›Each synch point has a name, and thread-ID Comments provide context (values from RTL) ›Often hand-edited during debug Example: [1536] read_rule thread_A # addr=h8a34 data=h1578 [1544] write_rule thread_B # addr=h8a34 data=h5343 [1632] read_rule thread_A # addr=h8a34 data=h5343 [1694] write_rule thread_B # addr=h8a34 data=hf519 [1694] read_rule thread_A # addr=h8a34 data=hf519

9 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM “Synchronized” Flow C-sim RTL-sim Compare csim.log rtl.log test.script

10 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Simulation Kernel Read Synch Read Stimulus [pending] [not pending] Call Synch function Pending Synch Points (task list)

11 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Memory Access with Arbiter A B Arb Mem Monitor Delay

12 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Dual Port Memory Access Monitor AMonitor B A B Memory Delay

13 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM int field = extract(rule, packet_data); interpret(rule, field, &result, &rule_address); } return result; } A Functional Model } int continue_read_rule () { int classify_packet ( Packet packet_data, Uint32 rule_address ) { int result = ITERATE while (result == ITERATE) { RuleStruct rule; read_rule(&rule, rule_address);

14 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Refactoring 1.Move local variables into a “context” structure. Create an instance (on the heap, not the stack) at start of transaction – and delete at end. 2.Replace iterative loops with recursive functions. 3.For each function that requires synchronization (directly or indirectly), replace the call with a request/callback pair.

15 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM “Context” Structure struct context { Packetpacket_data; Uint32rule_address; RuleStructrule; intfield; intresult; void(*callback) (int); };

16 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Introduce Context Structure void classify_packet_request ( Packet packet_data, Uint32 rule_address, void (*callback)(int)) { struct context *cxt = calloc(1, sizeof(struct context)); cxt->packet_data = packet_data; cxt->rule_address = rule_address; cxt->callback = callback; cxt->result = ITERATE; classify_packet_iterate(cxt); } void packet_classify_reply(struct context *cxt) { int result = cxt->result; void (*callback)(int) = cxt->callback; free(cxt); callback(result); }

17 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Non-Recursive Implementation void classify_packet_iterate ( struct context *cxt ) { while (cxt->result == ITERATE) { read_rule(&cxt->rule, cxt->rule_address); cxt->field = extract(cxt->rule, cxt->packet_data); interpret(cxt->rule, cxt->field, &cxt->result, &cxt->rule_address); } classify_packet_reply(cxt); }

18 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Recursive Implementation void classify_packet_iterate ( struct context *cxt ) { if (cxt->result == ITERATE) { read_rule(&cxt->rule, cxt->rule_address); cxt->field = extract(cxt->rule, cxt->packet_data); interpret(cxt->rule, cxt->field, &cxt->result, &cxt->rule_address); classify_packet_iterate(cxt); } else { classify_packet_reply(cxt); } }

19 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Synchronized Implementation void classify_packet_iterate ( struct context *cxt ) { if (cxt->result == ITERATE) { read_rule_request(&cxt->rule, cxt->rule_address, &classify_packet_continue); } else { classify_packet_reply(cxt); } void continue_read_rule ( struct context *cxt ) { cxt->field = extract(cxt->rule, cxt->packet_data); interpret(cxt->rule, cxt->field, &cxt->result, &cxt->rule_address); classify_packet_iterate(cxt); }

20 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Transaction Diagrams Extract Interpret Read Rule [done][iterate] Rules DB Packet Buffer Classify Packet

21 © 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM Part 2 Patterns in Transaction Synchronization

22 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Adding a Cache ›Cache needn’t effect transactions Data-RAM not modeled cache is coherent Can rerun all tests, with no changes to C model ›Tag RAM is an Addition, not Modification Independent Transactions Independent Synchronization

23 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Single Port, Cached A B Arb Mem Read/Write Delay Cache Tag RAM Miss Rd/Wr Hit Rd/Wr Correct Errors Check ECC

24 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Cache Transaction (Read) Read Data [hit] Write Tag Read Tag [miss] Write Tag Check ECC

25 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM FIFOs and Counters ›Delay elements need no synchronization But synchronization can increase locality ›Some FIFOs can drop transactions Synchronize overflow: don’t model actual size ›Counters seem to need cycle-based model We want to avoid this ›Correct Synch propagates “forces” to Model

26 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Force Synchronizing a FIFO Flow Control ProducerConsumer FIFO PushPop Drop

27 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM FIFO Transaction Diagram [drop] [push] Pop

28 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM FIFO Synchronization Checker ProducerConsumer FIFO Push Pop Drop Checker: Queue Size Assertions

29 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Force value Counters Register +1 load Client UpdateSample value select clk sample_en

30 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Scaffolding ›Permit verification incomplete RTL Encourage end-to-end skeletons Implement “incorrect, but simple” algorithms Don’t wait for complete RTL Postpone modeling the algorithm Use synch to avoid chasing a moving target Remove scaffolding once RTL is complete

31 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM An Algorithm Cache Read Node Tree Search Node Memory Result Cache HitMiss Tag Ram Hit Rd/Wr Miss Rd/Wr

32 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Algorithm Cache: Transactions Read Node [match] [No match] [iterate] [hit] [miss] Backdoor search Read Tag

33 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Speculation ›When hardware speculates: Effect precedes cause Transaction model appears incorrect ›Creative accounting can sometimes help Insert a “virtual” delay Filter based on future events

34 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Speculation Read Ctrl Read Data

35 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Speculation Read Ctrl Read Data

36 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Speculative Reads Stage 1Stage 2 Stage 4Stage 3 Ctrl RAM Update Lookup (Pipe) write read Delay (2 clocks)? write read Data RAM Update advance (2 clocks)?

37 © 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM Part 3 Methodology, Futures, Summary

38 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Verification Flow ›RTL Simulation is expensive Licenses CPU time ›Post-Processing is cheap ›Stop simulations when broken But not if bug is in test/model

39 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Methodology ›Cycle-Precise Reference Comparison Without a cycle-accurate model ›Verify the System First Bringup Flow (Function Model) Synchronized Flow (Transaction-Testbench) ›Postpone module level testing Use scoreboarding to identify unit testbenches Only build unit-testbenches for stable modules

40 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Comparison with Platform-Based ›System-on-Chip Methodology Verify components first Verify system as composition of verified units ›Complex-ASIC Methodology Verify transactions first Verify units in context of verified transactions An “Agile” Methodology

41 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Future Work ›Performance in non-synchronized mode Use threading to avoid fragmentation ›Synchronization as basis of SW architecture Cycle-model plug-in could provide synch Can postpone this plug-in until tapeout ›But what if we want a cycle-model earlier? Example: up-front performance validation

42 © 2003 Fast-Chip Confidential. All rights reserved. 11/23/2015 3:37:34 AM Summay ›Cycle timing is a “Don’t Care” ›Initial verification uses “Functional” model Refactor into “Transaction” model ›RTL provides cycle timing Caches, like FIFOs, are just delay elements “Forces” in testbench propagate to model ›“Coarse-grain first” methodology

43 © 2003 Fast-Chip. All rights reserved. 11/23/2015 3:37:34 AM Questions mailto:Dave@Whipp.name http://Dave.Whipp.name/dv

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