1. The DRS2 Chip: A 4.5 GHz Waveform Digitizing Chip for the MEG Experiment Stefan Ritt Paul Scherrer Institute, Switzerland

2. 19 Oct. '04IEEE/NSS Rome 20042 The MEG Experiment at PSI Stopped  beam of 10 7 -10 8 s -1, 100% duty factor Liquid Xe calorimeter for  detection Solenoidal magnetic spectrometer Radial drift chambers for e + momentum determination Timing counter for e + Stopped  beam of 10 7 -10 8 s -1, 100% duty factor Liquid Xe calorimeter for  detection Solenoidal magnetic spectrometer Radial drift chambers for e + momentum determination Timing counter for e + E e = 52.8 MeV Kinematics  e  = 180° E g = 52.8 MeV e   97 98 99 00 01 02 03 04 05 06 07 PlanningR & DAssmbl.Data Taking Goal:  → e  at 10 -13 N7-4 T. Iawamoto N7-4 T. Iawamoto

3. 19 Oct. '04IEEE/NSS Rome 20043 Waveform Digitizing Needed: Pile-up rejection (BG from 10 8 µ decays in unsegmented calorimeter) ADC dynamic range of 12 bit TDC resolution of 40 ps Analog pipeline (L1 trigger) ~300ns 3000 channels Needed: Pile-up rejection (BG from 10 8 µ decays in unsegmented calorimeter) ADC dynamic range of 12 bit TDC resolution of 40 ps Analog pipeline (L1 trigger) ~300ns 3000 channels t PMT sum 51.5 MeV 0.511 MeV ~100ns 2 GS 10 Bit 100€/Chn

4. 19 Oct. '04IEEE/NSS Rome 20044 The DRS chip: principle of operation Domino Ring Sampler

5. 19 Oct. '04IEEE/NSS Rome 20045 Design of Inverter Chain PMOS > NMOS PMOS < NMOS

6. 19 Oct. '04IEEE/NSS Rome 20046 “Tail Biting” enable 1234 1 2 3 4

7. 19 Oct. '04IEEE/NSS Rome 20047 Domino Speed Control URUR USUS URUR USUS Two independent voltages to control domino wave speed U R used to select speed range U s used for fine-adjustment Need to compensate temperature and V dd drifts Two independent voltages to control domino wave speed U R used to select speed range U s used for fine-adjustment Need to compensate temperature and V dd drifts

8. 19 Oct. '04IEEE/NSS Rome 20048 Current mode readout First implemented in DRS2 (DRS1 had charge readout) Sampled charge does not leave chip Current readout less sensitive to charge injection and cross-talk First implemented in DRS2 (DRS1 had charge readout) Sampled charge does not leave chip Current readout less sensitive to charge injection and cross-talk write read C (200fF)... R (700  ) I V out V in

9. 19 Oct. '04IEEE/NSS Rome 20049 Timing Reference signal 20 MHz Reference clock PMT hit Domino stops after trigger latency 8 inputs shift register Reference clock domino wave MUX Domino speed stability of 10 -3 : 400 ps uncertainty for full window 25 ps uncertainty for timing relative to edge Domino speed stability of 10 -3 : 400 ps uncertainty for full window 25 ps uncertainty for timing relative to edge

10. 19 Oct. '04IEEE/NSS Rome 200410 The DRS2 Chip Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm 2 Radiation Hard (CMS Pixel library, R. Horisberger) 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz) Maximal sampling speed 4.5 GHz Readout speed 40 MHz Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004 Packaged chip costs: 35 € / chn. (MPW run) 3 € / chn. (engineering run) Fabricated in 0.25  m 1P5M MMC process (UMC), 5 x 5 mm 2 Radiation Hard (CMS Pixel library, R. Horisberger) 10 channels (8 data + 2 calibration), each 1024 bins (300 ns analog delay + 100 ns signal at 2.5 GHz) Maximal sampling speed 4.5 GHz Readout speed 40 MHz Submitted to UMC in November 2003, 58 chips (400 channels) received in March 2004 Packaged chip costs: 35 € / chn. (MPW run) 3 € / chn. (engineering run) Domino Circuit Readout Shift Register 10 channels x 1024 bins

11. DRS2 Test Results Preliminary !

12. 19 Oct. '04IEEE/NSS Rome 200412 Measured DRS2 Parameters Linear response up to 400mV Usable range of 1V p-p Linear response up to 400mV Usable range of 1V p-p Speed range 0.5 GHz – 4.2 GHz Linear approximation

13. 19 Oct. '04IEEE/NSS Rome 200413 PLL Stabilization PLL External Common Reference Clock (1-4 MHz) V speed Reference ClockDomino Wave Pulse ~200 psec R. Paoletti, N. Turini, R. Pegna MAGIC collaboration R. Paoletti, N. Turini, R. Pegna MAGIC collaboration Unstabilized jitter: ~70ps / turn Temperature coefficient: 500ps / ºC Unstabilized jitter: ~70ps / turn Temperature coefficient: 500ps / ºC

14. 19 Oct. '04IEEE/NSS Rome 200414 Frequency stabilization V speed 16-bit DAC LUT FPGA Frequency Counter Compensate for temperature drifts Change Vspeed only between events, keep stable during acquisition phase Jitter ~ 150ps Timing accuracy with 9th channel < 25ps Compensate for temperature drifts Change Vspeed only between events, keep stable during acquisition phase Jitter ~ 150ps Timing accuracy with 9th channel < 25ps 150ps

15. 19 Oct. '04IEEE/NSS Rome 200415 Estimated Bandwidth Input pulse rising time: 0.9 ns Sampled at 2.5 GHz: 0.4 ns / sample Reconstructed rise time: 3 samples → 1.2 ns Estimated BW » 500 MHz Limited by protection diodes 40 MHz readout clock Direct DRS2 output

16. 19 Oct. '04IEEE/NSS Rome 200416 DAQ Boards DRS R. Paoletti, N. Turini, R. Pegna MAGIC collaboration USB PSI GVME Board FPGA with 4 Power-PC

17. 19 Oct. '04IEEE/NSS Rome 200417 Digitized Signals 7 ns pulses 500 mV Digitized at 2.5 GHz with USB test board 7 ns pulses 500 mV Digitized at 2.5 GHz with USB test board Pulses are nicely reproduced Analog inputs not properly terminated Non-constant response over 1024 cells (parasitic R of current readout on chip) Pulses are nicely reproduced Analog inputs not properly terminated Non-constant response over 1024 cells (parasitic R of current readout on chip) ns mV

18. 19 Oct. '04IEEE/NSS Rome 200418 Signal-to-noise ratio mV 1 V DC input signal, common mode subtracted Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit) Integration over 100 ns PMT pulse (250 bins) has RMS of 0.16 mV → SNR = 6200:1 (12.6 bit) Could be improved by better analog design of Mezzanine board 1 V DC input signal, common mode subtracted Individual bin has RMS of 2 mV → SNR = 500:1 (9 bit) Integration over 100 ns PMT pulse (250 bins) has RMS of 0.16 mV → SNR = 6200:1 (12.6 bit) Could be improved by better analog design of Mezzanine board

19. 19 Oct. '04IEEE/NSS Rome 200419 Waveform Analysis MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec Compress “interesting” and pile-up events in FPGA ( → 10x) Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data Overall data rate ~2 MB/sec MEG: 3000 channels, 100 Hz, 1024 samples → 600 MB/sec Compress “interesting” and pile-up events in FPGA ( → 10x) Fit “background” events in PC farm (~10 PCs) with individual PMT response functions, derive multi-hit ADC and TDC data Overall data rate ~2 MB/sec  Experiment 500 MHz sampling

20. 19 Oct. '04IEEE/NSS Rome 200420 Next generation: DRS3 DRS1DRS2 DRS3 Estimated First testedNovember 02March 04Fall 05 Number of channels11010 (all differential) Number of cells/channel76810241024-8192 MIN sampling speed (GHz)0.70.5 MAX sampling sped (GHz)2.54.5 Readout Speed (MHz)2040 Readout Dead Time (µsec)40256 (1024 samples)10 (40 samples) Signal to Noise ratio (bit)-> 12 (250 samples)> 12 Power Consumption (mW)2550 ?

21. 19 Oct. '04IEEE/NSS Rome 200421 Conclusions Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz Deploy ~200 channels in MEG Experiment in spring 2005 Use DRS2 for drift chamber readout Final version (DRS3, 3000 channels) in 2006 Not specific to MEG, useful for other experiments Successful design of DRS2 with 8 x 1024 bins, running at 4.5 GHz Deploy ~200 channels in MEG Experiment in spring 2005 Use DRS2 for drift chamber readout Final version (DRS3, 3000 channels) in 2006 Not specific to MEG, useful for other experiments