1. MS IPHC-LBL phone meeting, July 10, 2012 1 1 1 Ladder Testing at IPHC and LBL

2. MS IPHC-LBL phone meeting, July 10, 2012 2 2 Outline Synchronization of the ladder Ladder L1 operated in SYNC Ladder L2 (LBL) no SYNC Sensor with a faulty output Summary

3. MS IPHC-LBL phone meeting, July 10, 2012 3 3 Synchronization of the ladder Sync sequence: 1. Stop the main CLK 2. RSTB 3. JTAG configuration 4. Enable the main CLK 5. START Enable/disable CLK by using synchronous OE in the PLL device (CY7B9950) – A relatively small patch in the existing hardware – A small modification in the new MTB board design  As suggested by Gilles OE Ladder CLK

4. MS IPHC-LBL phone meeting, July 10, 2012 4 4 Ladder L1 operated in SYNC

5. MS IPHC-LBL phone meeting, July 10, 2012 5 5 L1 – “full” decoupling + SYNC A small mystery – Single sensor – very noisy ? – One of ten – OK

6. MS IPHC-LBL phone meeting, July 10, 2012 6 6 Chip 6 – HIGH Chip 2 – HIGH Chip 1 – HIGH Normal readout mode (20 RSTB x 5 START) Stable readout Same cut settings for LOW and HIGH threshold operation  Clearly, two different operating points Chip 1 – LOW Chip 2 – LOW Chip 6 – LOW

7. MS IPHC-LBL phone meeting, July 10, 2012 7 7 L2 – tested at LBL (“full” decoupling, no sync) Good repeatability – tested x10 for each sensor, but… issues in the normal readout mode Fit problems

8. MS IPHC-LBL phone meeting, July 10, 2012 8 8 Sensor with a faulty output L1 chip 4 MTB output 5.2 - green MTB output 5.1 - red Output delay: – @160 MHz Tx=40  7.4 ns – @160 MHz Tx=100  3.3 ns – @ 50 MHz Tx=40  7.2 ns – @ 50 MHz Tx>100  3.0 ns – @ 50 MHz Tx=20  12.6 ns patt mode, no cnt, header FFFF, trailer EEEE, TX=40 AAFF, TX=40AAFF, TX=100 AAFF, TX=100, 10 ns/div

9. MS IPHC-LBL phone meeting, July 10, 2012 9 9 Summary Synchronization problem has been solved – IPHC solution: stop CLK, RSTB, JTAG, enable CLK, START – CLK enable/disable via PLL synchronous OE  minor modifications in the PXL hardware – Why is it different than in Phase-1 ? L1 (IPHC) – Good noise performance with decoupling capacitors and in sync – Stable readout in the normal readout mode – Small noise degradation @ LOW thresholds L2 (LBL) – Similar noise performance to L1 – To be tested in SYNC – Degraded performance using “sense” regulators – under investigation