1. PHY 202 (Blum)1 Combinations of Resistors Series, Parallel

2. PHY 202 (Blum) 2 Analyzing a combination of resistors circuit Look for resistors which are in series (the current passing through one must pass through the other) and replace them with the equivalent resistance (R eq = R 1 + R 2 ). Look for resistors which are in parallel (both the tops and bottoms are connected by wire and only wire) and replace them with the equivalent resistance (1/R eq = 1/R 1 + 1/R 2 ). Repeat as much as possible.

3. PHY 202 (Blum) 3 Look for series combinations R eq =3k  R eq =3.6 k 

4. PHY 202 (Blum) 4 Look for parallel combinations R eq = 1.8947 k  R eq = 1.1244 k 

5. PHY 202 (Blum) 5 Look for series combinations R eq = 6.0191 k 

6. PHY 202 (Blum) 6 Look for parallel combinations R eq = 2.1314 k 

7. PHY 202 (Blum) 7 Look for series combinations R eq = 5.1314 k 

8. PHY 202 (Blum) 8 Equivalent Resistance I = V/R = (5 V)/(5.1314 k  ) = 0.9744 mA

9. PHY 202 (Blum) 9 Backwards 1 V= (3)(.9744) = 2.9232 V= (2.1314)(.9744) = 2.0768

10. PHY 202 (Blum) 10 Backwards 2 V = 2.0768=I (3.3) I=0.629mA V = 2.0768=I (6.0191) I=0.345mA

11. PHY 202 (Blum) 11 Backwards 3 V=(.345)(1.1244)=0.388 V=(.345)(1.8947)=0.654 V=(.345)(3)=1.035

12. PHY 201 (Blum) 12 Multiplexing and Demultiplexing In some sense, Multiplexing and Demultiplexing is just a special case of the truth tables we have been studying. You can look under “multiplexor” and “decoder” in the index of Tokheim for more information.

13. PHY 201 (Blum) 13 Getting Around A fair amount of what goes on inside computers or on computer networks just involves moving data (as opposed to processing that data). Most designs have shared information channels (a bus). Part of the path used to get from Point A to Point B may also be along the way from Point C to Point D. Multiplexing and demultiplexing concerns selecting the data to be transmitted and directing the data to its destination.

14. PHY 201 (Blum) 14 Multiplexing Multiplexing is sending more than one signal on a carrier. There are two standard types of multiplexing. Frequency-Division Multiplexing (FDM): the medium carries a number of signals, which have different frequencies; the signals are carried simultaneously. Time-Division Multiplexing (TDM): different signals are transmitted over the same medium but they do so at different times – they take turns.

15. PHY 201 (Blum) 15 Mutiplexing Multiplexing allows one to select one of the many possible sources.

16. PHY 201 (Blum) 16 Statistical TDM In standard TDM, the inputs take turns, one after the other gets to put its information onto the wire. In Statistical TDM, the input with the most data or highest priority gets a higher share of the time. In this course, our wires hold a single bit of information at a time, so we will focus on a simple type of TDM. It will be somewhat more like statistical TDM in that we will be choosing which input places its information on the wire.

17. PHY 201 (Blum) 17 Multiplexing There are several data inputs and one of them is routed to the output (possibly the shared communication channel). Like selecting a television channel (although that example is FDM). In addition to data inputs, there must be select inputs. The select inputs determine which data input gets through. How many select pins are needed? Depends on number of data inputs.

18. PHY 201 (Blum) 18 Addresses All of the (data) inputs at hand are assigned addresses. The address of the data input is used to select which data input is placed on the shared channel. So in addition to the collection of data inputs, there are selection (or address) inputs that pick which of the data inputs gets through.

19. PHY 201 (Blum) 19 How many? One bit can have two states and thus distinguish between two things. Two bits can be in four states and … Three bits can be in eight states, … N bits can be in 2 N states 000 001 010 011 100 101 110 111

20. PHY 201 (Blum) 20 Nomenclature A Multiplexer is also known as a MUX. A MUX has several data inputs and one data output. If the MUX has N (possible) data inputs, it is referred to as an N-to-1 MUX. Since computers work in binary, the N is usually a power of 2. An N-to-1 MUX should have log 2 (N) address inputs (pins).

21. PHY 201 (Blum) 21 Log 2 (N) N 21 42 83 164 325 646 1287 2568 NLog 2 (N) 5129 102410 204811 409612 819213 1638414 3276815 6553616

22. PHY 201 (Blum) 22 Combinatorial Logic A MUX uses combinatorial logic (as opposed to a sequential logic which involves memory). The output of a MUX depends solely on the data input and the select input. Thus it is just the realization of a truth table.

23. PHY 201 (Blum) 23 Truth table for 2-to-1 MUX SelectData Out AD0D1 0000 0010 0101 0111 1000 1011 1100 1111 When A=0, Out is same as D0, when A=1, Out is same as D1

24. PHY 201 (Blum) 24 Algebra for 2-to-1 MUX Take expressions for 1’s found in truth table AD 0 D 1 + AD 0 D 1 + AD 0 D 1 + AD 0 D 1 This can be factored as follows AD 0 (D 1 +D 1 ) + A(D 0 +D 0 )D 1 (D 1 +D 1 ) = 1 Not D 1 or D 1, doesn’t care about D 1 Note that this factoring/reducing requires the two terms to differ by only one input. AD 0 + AD 1 (A more general technique for simplifying Boolean expressions uses the Karnaugh map.)

25. PHY 201 (Blum) 25 Karnaugh Version AB\S01 0000 0101 1111 1010

26. PHY 201 (Blum) 26 Gates for 2-to-1 MUX

27. PHY 201 (Blum) 27 4-to-1 MUX: truth table SelectData Out ABD0D1D2D3 00D0D1D2D3D0 01 D1D2D3D1 10D0D1D2D3D2 11D0D1D2D3 D0 could be a 1 or a 0, but if A=0 and B=0 then Out is whatever D0 is.

28. PHY 201 (Blum) 28 4-to-1 MUX: gate version Many inputs One output

29. PHY 201 (Blum) 29 Addresses Each data input is assigned to a specific state of the select input. E.g. low-low, low-high, high-low, high-high The state can be interpreted as binary numbers 00, 01, 10, 11 Two select  Four addresses And these numbers are thought of as the “addresses” of the input.

30. PHY 201 (Blum) 30 Demultiplexing If any of several signals was put onto a single carrier, then at the other end the signals must be separated and each sent to the appropriate destination. One input (the shared channel) is routed to one of several outputs. Like mail, it is possible for me to send a message to any individual one of you. So there must be a set of paths from me to each of you, and there must be a mechanism for selecting one of those paths in a particular instance. In addition to data input, there must be select inputs. To select from 2 N data outputs requires N select inputs.

31. PHY 201 (Blum) 31 Demultiplexing Demultiplexing allows one to select one of the many possible destinations.

32. PHY 201 (Blum) 32 Nomenclature Demultiplexer a.k.a. DeMUX. A DeMUX has one data input and several outputs. If the DeMUX has N (possible) data outputs, it may referred to as an 1-to-N DeMUX. Since computers work in binary, the N is usually a power of 2. An 1-to-N DeMUX should have log 2 (N) address inputs (pins). DeMUX are also sometimes referred to by the number of address pins log2(N)-to-N DeMUX (e.g. 3-to-8 or 2-to-4 DeMUX)

33. PHY 201 (Blum) 33 Combinatorial Logic A DeMUX has many outputs. Each of those outputs depends only on the input data and the select data (i.e. no memory is involved). Thus a DeMUX is just a realization of a truth table (as is all combinatorial logic).

34. PHY 201 (Blum) 34 1-to-4 DeMux: Truth table SelectDataOutput S1S0AO0O0 O1O1 O2O2 O3O3 0000000 0011000 0100000 0110100 1000000 1010010 1100000 1110001

35. PHY 201 (Blum) 35 1-to-4 DeMUX: gate version (may also be called 2-to-4) One input Many outputs

36. PHY 201 (Blum) 36 Decoder A variation on the previous circuit is to have no input data. The selected output will be high, the others low. Or vice versa. This can be used to activate a control pin on the selected part of circuit.

37. PHY 201 (Blum) 37 2-to-4 Decode: Truth table SelectOutput S1S0O0O0 O1O1 O2O2 O3O3 001000 010100 100010 110001

38. PHY 201 (Blum) 38 2-to-4 Decode: gates

39. PHY 201 (Blum) 39 Decoder plus registers = RAM A register is a unit of memory that holds one word of data. A typical word may be 32 or 64 bits. E.g. the Memory Address Register (MAR) holds an address associated with memory Memory (RAM), on the other hand, is a large collection of registers to hold the values of many different words. In addition to the registers is a decoder. The decode determines which word one is writing to or reading from.

40. PHY 201 (Blum) 40 Decoder plus registers = RAM Decoder MDR MAR Load pins (allow data into a register) Addressable set of registers MAR: Memory Address register holds address one is writing to or reading from MDR Memory data register holds data being written to or being read from memory. Only one location selected.

41. PHY 201 (Blum) 41 ROM is Combinatorial In ROM (Read Only Memory), one inputs an address and gets a predetermined output for that address. The same input always yields the same output. ROM is the realization of a truth table. ROM is a way to realize a generic truth table. In a way the opposite of what we do with a Karnaugh map. With a K-map we take a specific output and simplify it as much as possible. With ROM, we leave it as generic as possible.

42. PHY 201 (Blum) 42 The logic of ROM Decoder Address lines fuse “Burned” fuse

43. PHY 201 (Blum) 43 Logic of ROM (Cont.) Fuses connect output of decoder to output of ROM. Normal voltage and current does not burn (“blow”) the fuse. So when the selected decoder output is high, all ROM output lines to which it is connected are also high.

44. PHY 201 (Blum) 44 Logic of ROM (Cont.) Higher voltage and current will break the connections (a.k.a. burning). They are applied selectively to break certain connections. The ROM output is not affected by the decoder output if the connection is broken. (Implementation may be different, but this is the basic logic).