1. 2012. 06. 13 Miseon Han Thomas W. Barr, Alan L. Cox, Scott Rixner Rice Computer Architecture Group, Rice University ISCA, June 2011

2. Motivation

3. Virtual memory – Performance overhead 5-14% for ‘typical’ applications [Bhargava08] – 89% under virtualization [Bhargava08] – Large pages not always a good solution 3

4. What page size to pick? – 4KB, 2MB, 1GB on x86 Can’t always use largest size – Wasted memory – increased I/O traffic Dynamic page size selection 4

5. SpecTLB (Speculative TLB) – A hardware/software system Reservation-based physical memory allocator [Talluri94] – Allocate small pages by default to maintain fine-grained control Predict small page translations in hardware – Performance of large pages, control of small pages 5

6. Background

7. Four-level radix-tree page table 7 0x5c8315cc2016 [47:39] [38:30] [29:21] [20:12] [11:0] {0b9, 00c, 0ae, 0c2, 016} {123, 016}

8. Page table levels describe physical address space at different granularity 8 512GB1GB2MB4KB

9. Reservation-based memory allocation [Talluri94] – Always allocate small pages in book-keeping entry at first – Place these small pages in a large page ‘reservation’ if the handler decides that reservation is needed – Promote reservation to large page when all small pages in the reservation are allocated – Extended and implemented in FreeBSD [Navarro02] Default memory allocator 9

10. 10 Handler reserves 2MB region of physical space

11. 11 Reservation is ‘promoted’ into Large page.

12. 12 Reservations may not be filled.

13. 13

14. SpecTLB

15. TLB-like structure – Tracks reservations, not actual mappings – Detect reservations – Predict translations – Verify predictions 15

16. 16 {0b9, 00c, 0ae, 002, 313}{8002, 313} Virtual AddressPhysical Address {0b9, 00c, 0ae, 000, 000}{8000, 000} Current Reservations: {8000, 000}

17. 17 {0b9, 00c, 0ae, 005, 313}{8005, 313}? Virtual AddressPhysical Address {0b9, 00c, 0ae, 000, 000}{8000, 000} Current Reservations: {8000, 000} ?

18. Provides predicted translations for pages within tracked reservations Predictions may be incorrect – Page table must still be walked Page walk can occur in parallel Latency hidden – Speculative translation can be used concurrently Microarchitecture cancels speculative work 18

19. Simulation & Result

20. BenchmarkTLB miss rate (/1k DRAM accesses) Speculative Prediction frequency Prediction Accuracy DRAM Accesses Overlapped PostgreSQL74.430.7620.9890.448 python15.360.7600.9980.419 SPECjbb20.040.4180.9710.310 bzip24.000.2930.9980.235 gcc4.250.8520.9880.664 mcf79.430.9921.0000.956 dc.B42.290.0830.3530.073 ep.C12.940.0140.9620.023 20 Full system simulator, unmodified FreeBSD kernel

21. SpecTLB and TLB prefetching hide the latency of TLB misses. – SpecTLB : large-page reservations. current TLB miss. – TLB prefetcher : access patterns, future TLB miss. Speculative work – SpecTLB : instructions are executed parallel with translation confirm. – TLB prefetcher : prefetch page table entries. 21

22. Generally hides fewer walks than SpecTLB – Prefetcher does well with high access regularity 22 BenchmarkTLB miss rate SpecTLBTLB Prefetcher PostgreSQL74.430.9890.106 python15.360.9980.633 SPECjbb20.040.9710.151 bzip24.000.9980.978 gcc4.250.9880.330 mcf79.431.0000.051 dc.B42.290.3530.190 ep.C12.940.9620.897

23. SpecTLB hides latency of TLB misses – Predictions allow page walk to occur in parallel with speculative work – >62% of TLB miss latencies hidden for majority of benchmarks 23