1. Rinoy Pazhekattu

2. Introduction  Most IPs today are designed using component-based design  Each component is its own IP that can be switched out for different components if needed  Components are responsible for a small subproblem of a larger problem 1

3. Component-based IPs  Number of benefits to component based design Can modify each component individually Reliable since each component is from a trusted source Components can be reused in other designs 2

4. Why evolvable IPs  Components cannot be upgraded quickly after manufacturing  Some applications must adapt to varying environments  What if there was a way to modify IPs immediately after a better solution was found?  This is possible using evolvable IPs 3

5. Background of Evolvable IPs  Evolvable IPs are IPs that can improve their performance overtime  This is done by constantly finding better solutions  Current best solution is used until better one found  Can implement evolvable IPs using current technologies 4

6. Evolvable IP on an FPGA 5

7. Implementation Methods  Must be a partially reconfigurable circuit  Use genetic algorithms to find a better solution  Virtual reconfigurable circuits are used to simulate and test the new solutions 6

8. Genetic Algorithms  Uses a population of solutions that are constantly improving to find optimal solutions  Fitness function is used to compare generated solutions to current best  Mutations generate more solutions as well as crossing between the best solutions 7

9. Virtual Reconfigurable Circuits  A reconfigurable circuit that can be configured and implemented by the slices on the FPGA  Consists of a set of Configurable Functional Blocks(CFBS)  Essentially a partial reconfigurable circuit 8

10. Configurable Functional Blocks  CFBs implement simple functions and can switch between them  A number of bits can select between different functions  Other bits used to specify routing  Multiplexers used to select between functions and for routing bits 9

11. Example of a CFB 10

12. Genetic Unit and Controller  Can either be implemented as specialized hardware or using a microprocessor  Communicates with environment to perform genetic operations on chromosomes  Also responsible for reconfiguring the virtual circuit 11

13. Example Applications  Image filtering or DSP applications can benefit from evolvable IP cores  An adaptive image filter is examined implemented as an evolvable IP core on Virtex slices 12

14. Adaptive Image Filtering  Input is represented by 8 bits/pixel, and output is also 8 bits  Nine 8-bit input lines I0-I8 and one 8-bit output line fout  Processes pixels in a 8-stage pipelined softcore on an FPGA  Can adapt to different environments to remove noise from the image using evolvable IPs. 13

15. CFBs for Image Filtering  29 CFBs are used for the adaptive image filter  Use 4 bits to select function of CFB  Input to CFBs comes from a set of six registers 14

16. CFBs for Image Filtering  Sixteen 16-input multiplexers are used to set the routing of the CFBs  Function selection of CFBs is stored in reconfiguration memory 15

17. Genetic Unit and Controller  Genetic unit is implemented on a softcore such as Microblaze or Picoblaze  Fitness calculation and evolution carried out on Microblaze  Uses population of 4 individuals with single bit mutations 16

18. Genetic Unit and Controller  Also responsible for reconfiguring the virtual reconfigurable circuit  Following structures used: Chromosome memories Fitness registers Mutation unit Two control counters Finite State Machine 17

19. Genetic Unit Example 18

20. Adaptive Image Filter Top Level 19

21. Results  Number of image operators were evolved through software simulations  Shown to be competitive with conventional filters  More time lead to better adapted solution to filter noise  Evolution accelerated 70 times by carrying out fitness calculation on physical circuit 20

22. Camea DX6 Board  Customized board specifically for implementing evolvable IPs  Has a VLIW DSP processor  Virtex FPGA  128 MB of operational memory  Additional customizations for implementing evolvable cores 21

23. Criticism  Advantages In general, the technique can be very useful for certain applications Being able to improve circuit function in realtime is beneficial  Disadvantages Can only be realized on an FPGA and not an ASIC Determining how many CFBs to use and what functions they should provide can be difficult 22

24. Conclusions  Evolvable IP cores can be useful for designing adaptive systems  Implementing evolvable cores on hardware can significantly improve evolution time  A component-based method for designing evolvable IPs was shown  FPGAs today can be used to implement evolvable IPs as reconfigurable circuits 23

25. References  Sekanina L. Towards Evolvable IP Cores for FPGAs. Proceedings of The 2003 NASA/Dod Conference on Evolvable Hardware, 2003. 24