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Edward Freeman CCLRC ESDG Optical Data Acquisition Development EID forum 12th October 2005 By Edward Freeman
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Edward Freeman CCLRC ESDG Introduction to Optical data acquisition High speed Standard off the shelf backend Low cost and reusable design blocks Configuration and control and readout Electrically isolated from PC and world Operate over local network or the internet
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Edward Freeman CCLRC ESDG Ethernet basics Protocol dataHeaderCRC Header at lest 22 bytes CRC = cyclical redundancy check = 4 bytes Protocol data is 46-1500 bytes Each layer of abstraction adds its own header and check sum UDP/IP is about the simplest protocol robust enough to go across the internet. Qxtream is a small over head on top of UDP/IP An Ethernet packet
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Edward Freeman CCLRC ESDG Performance for 1Gb system Benchmarked - 65 Mbyte/s sustained FPGA - PC Software Histogramming 5 Mwords/s sustained (bottlenecked by software and PC)
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Edward Freeman CCLRC ESDG Main features of the system Power, temp. and FPGA monitoring with the CPLD Battery for triple DES keys to protect IP Re-configure FPGA PROM’s over internet Fall back PROM’s Ethernet UDP/IP interface Fail safe shut down on errors Point of load power regulation Works with Development boards Put a nice pic here!
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Edward Freeman CCLRC ESDG System Design Overview UDP core DP_RAM RDMA Custom logic for user application Rx stream Tx stream FPGA Done pin CPLD Power Enable LM82 I2C PROM x 4 Done pin Programming pins JTAG JTAG control Fibre optic User IO
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Edward Freeman CCLRC ESDG The CIQE Stick Top Box The two connections to the outside world are the fibre optic and power cables The optical data acquisition FPGA part is the section high lighted in red
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Edward Freeman CCLRC ESDG The Test Set-up in Operation The stick is bathed in liquid helium to approximate the conditions at the 4K point in the full dilution fridge system The STB can just about be seen sticking out the top of the dewar
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Edward Freeman CCLRC ESDG Software Interface This interface is made in Matlab using the GUI creation tool C/C++, Matlab and Labview use a C++ dll that provided the interface to the Ethernet line card Matlab interface designed by Quentin Morrissey
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Edward Freeman CCLRC ESDG Remote RE-Configuration User interface designed by Steve Martin Front end of the reconfiguration tool This combined with the triple DES function provide a secure firmware distribution method
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Edward Freeman CCLRC ESDG OPTO DAC Project PC - PC PC - FPGA FPGA - FPGA ? VII Pro X loan 10 G XFP 10G EMAC
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Edward Freeman CCLRC ESDG List of projects using the optical data acquisition system CIQE MAPS MI3 OPIC MI3 Opto DAQ DIFFEX OPIC Intelligent Pixel Sensor MI3 project Jamie Crooks Already running About to start PETTRA Neural Imaging Laser Tweezers DAE III - ISIS Linear Collider R&D T2K Sorry about all the acronyms but there project names
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Edward Freeman CCLRC ESDG Scales to large systems with ease A large networks of small readout blocks can be created with off the self rack mount PC’s and switches This provided the advantages of custom firmware where the speed is needed the flexibility of software processing and standard interconnects
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