1. Hardware Implementation of a Signaling Protocol Polytechnic University Center for Advanced Technology in Telecommunications Haobo Wang Malathi Veeraraghavan Ramesh Karri

2. Outline Background and problem statement Hardware signaling – Why and how? A signaling protocol and its hardware implementation  Messages, data tables, procedures…  Hardware platform, state transition diagram… Conclusion and future work

3. What is a signaling protocol?  Set up and tear down connections in connection- oriented networks Signaling protocols are primarily implemented in software  Two reasons: Complexity and flexibility  Cost: Performance Problem statement of this work  Implement signaling protocol in reconfigurable hardware Background and problem statement

4. Low call setup delay - 4 us per switch  Fast restoration High throughput – 150,000 calls/sec  Support large scaled core switches – TCP switching Why hardware signaling

5. Challenges of hardware signaling For a hardware-oriented signaling protocol  Maintain per connection state  Many data table manipulations  Lots of messages, parameters, procedures  Resource management For CR-LDP  TLV

6. Our approach to hardware signaling Partition signaling functions  Hardware: common and simple functions  Software: infrequent and complex functions Use reconfigurable hardware – FPGA to solve the problem of flexibility

7. IP 5.7.2.1 IP 7.4.1.4 IP 5.7.2.3 IP 7.4.1.2 IP 4.8.2.1 Network and node view

8. We defined four messages Setup Setup Success Release Release Confirm Message LengthCause Msg.Type (0100) Connection Reference (prev.) Connection Reference (own) ReservedChecksum Message LengthTTL Msg.Type (0001) Connection Reference (prev.) Destination IP Address Source IP Address Previous Node’s IP Address BandwidthReservedInterface NumberTimeslot Number ReservedChecksum Message LengthCause Msg.Type (0011) Connection Reference (prev.) Connection Reference (own) ReservedChecksum Connection Reference Message Length Bandwidth Msg.Type (0010) Connection Reference (prev.) Connection Reference (own) ReservedChecksum

9. And five tables IndexReturn Value Destination Address Next Node Address Next Node Interface IndexReturn/Written Value Next Node Address Total Bandwidth Available Bandwidth IndexReturn Value Neighbor Address Neighbor Interface# Own Interface # Routing table CAC table Connectivity table State table Switch mapping table IndexReturn/Written Value Own Connection Reference Connection Reference State Band- width Node Address Previous Next Previous Next IndexReturn/Written Value Own Conn. Reference Sequential Offset Incoming Ch. ID.Outgoing Ch. ID. Interface#Timeslot#Interface#Timeslot#

10. IP 5.7.2.1IP 7.4.1.4 IP 5.7.2.3 IP 7.4.1.2 IP 4.8.2.1 IndexReturn/Written Value Cxn. Ref. Cxn. Ref. StateBW IP Address Prev.NextPrev.Next 124103115.7.2.37.4.1.2 IndexReturn/Written Value Cxn. Ref. Offset IncomingOutgoing Int.#TS.#Int.#TS.# 121510312 Connectivity table Int.#1 Int.#5 Int.#3 Int.#10 IndexReturn Dest.Addr.Next Hop Addr.Next Hop Int. # 7.4.1.47.4.1.23 Routing table IndexReturn/Written Next Hop Addr.Total BW.Available BW. 7.4.1.232->1 CAC table State table Switch mapping table IndexReturn Nghbr.Addr.Nghbr.Int.#Own Int.# 5.7.2.315 Processing of Setup message

11. Hardware platform – Wildforce

12. State transition diagram of signaling hardware accelerator

13. Timeslot manager 10001100 15 14 13 123 2 1 0 … … … …… 0 1 2 3 60 61 62 63 000011 Priority Decoder 1110 11001000 … 1100 1 100 … Output timeslot Scratch register Interface number 1100 marked as used Write back

14. The simulation results Simulation result for Setup message Simulation result for Setup Success message Simulation result for Release message Simulation result for Release Confirm message

15. …more words Assuming a 25 MHz clock  Total setup and teardown time: 5.9 to 6.8 us  Call handling capacity of 150,000 calls/sec Setup Setup Success Release Release Confirm Clock cycles 77-101*95110 * Based on a worst-case search through a four option routing table DeviceResourceEq.Gates CPE0 XC4036XLA 62%22,000 PE1XC4013XLA8%1,000

16. Feasibility  Yes, hardware signaling is possible if we implement the common and simple operations in hardware and infrequent and complex operations in software Advantage  100x-1000x speedup vis-à-vis software implementations Future work  GMPLS, applications Conclusion and future work

17. Thank your all! Please visit our website for more details, http://eeweb1.poly.edu/networks/html-files/hw_sig.htm

18. Any questions?