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MIT Lincoln Laboratory 999999-1 XYZ 3/11/2005 1 Hardware Based Floating Point Processing All the ingredients for FPGA based floating point –28 nm Variable.

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Presentation on theme: "MIT Lincoln Laboratory 999999-1 XYZ 3/11/2005 1 Hardware Based Floating Point Processing All the ingredients for FPGA based floating point –28 nm Variable."— Presentation transcript:

1 MIT Lincoln Laboratory 999999-1 XYZ 3/11/2005 1 Hardware Based Floating Point Processing All the ingredients for FPGA based floating point –28 nm Variable Precision DSP Block 28nm silicon enhancements for floating point –IP: Fused Datapath: efficient floating point in Altera FPGAs –Tools: DSP Builder Advanced Blockset Matlab/Simulink native support is floating point Cholesky decomposition / matrix inversion design –Programmable in both matrix size and vector size Ex: 20x20 with vector size of 10, 240x240 with vector size of 60 –Up to 1 Million matrices per second in a single core for time interleaved 20x20 matrices, multiple cores possible in single device Floating point roadmap –Silicon / Tools / IP

2 MIT Lincoln Laboratory 999999-2 XYZ 3/11/2005 2 Single Channel Results: Single Core Single Channel Cholesky Inversion Core Matrix Size Vector Size Dot Product Utilization Throughput (matrices/sec) Latency (us) 240x2406090.1%3282489 200x2005088.3%4619349 100x1005057.4%17,70097.8 75x755040.7%24,90066.7 50x505024.8%37,40041.3 100x1002570.3%14,400110.8 75x752552.5%22,80070.2 50x502531.2%37,20041.5 25x252512.9%73,80019.4 Multiple single precision Cholesky cores may be implemented within a single FPGA

3 MIT Lincoln Laboratory 999999-3 XYZ 3/11/2005 3 Multi-channel Results: Single Core Multi-Channel Cholesky Inversion Core Matrix Size Vector Size Number of channels Dot Product Utilization Throughput (matrices/sec) Latency (us) 100x10050696.8%29,900380 50x50502098.3%148,000270 75x75251098.3%42,700392 50x50252098.7%118,000304 25x25252095.6%526,00071 20x20205097.8%1,000,00096 Multiple single precision Cholesky cores may be implemented within a single FPGA

4 MIT Lincoln Laboratory 999999-4 XYZ 3/11/2005 4 Cholesky Throughput per FPGA device Cholesky Throughput per Stratix V FPGA Matrix Size Vector Size Device: Stratix V 5SGSD8 Number of cores per FPGA Throughput per core (matrices/sec) Throughput per FPGA device (matrices/sec) 20x2020single die, 700 kLE, 4000 mults 181M18 Million 240x2406063,00018 Thousand Multiple Cholesky cores implemented within a single FPGA

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