1. STA with Variation 1

2. 2 Corner Analysis PRCA (Process Corner Analysis):  Takes 1.nominal values of process parameters 2.and a delta for each parameter by which it varies.  Finds −performance as max and min values. Pros:  Simple Cons:  Conservative  Inaccurate  Inefficient: Not practical for many parameters Δ = 3σ

3. 3 Corner Analysis: Conservative & Inaccurate PRCA shortcoming:  Process corners are assumed to coincide with performance corners. −Fact: best/worst-case corner may not depend on P min or P max for a particular interconnect parameter but on a value within that range.

4. Corner Analysis: Conservative & Inaccurate  -35% to 75% impact on delay?! ParameterDelay Impact Metal (mistrack, thin/thick track)-10% to +25% Environmental (IR drop, temperature) +25% V th, t ox ±5% PLL (jitter, duty cycle, phase error)±10% N/P mistrack±10% Pessimistic Analysis:  Design that operates faster than necessary but high power consumption 4

5. Corner Analysis: Inefficient Inefficient / impractical (if you want to be exact):  Needs 2 n STAs / corner files −n: # of sources of variations −2 7 to 2 20 analyses in practice  Has long been done for inter-die variations −Small # of corner files 5

6. Corner Analysis: Inaccurate Inaccurate:  Cannot provide design sensitivity to different process parameters −Useful for robust design (i.t.o. timing yield) 6

7. Corner Analysis: Inaccurate STA with worst-case says these are equivalent: 7

8. Solution: SSTA SSTA:  Allows to compute the probability distribution of the design slack in a single analysis.  If (timing constraint - delay critical_path ) > 200 ps  yield ≈ 100%  If (delay critical_path - timing constraint) > 300ps  yield ≈ 0  Can adjust yield during design process 8 -

9. 9 Impact of Variation Importance of variation:  Timing violations −  Yield loss 9

10. 10 Impact of Variation Process variations can cause  up to 2000% variation in leakage current and  30% variation in frequency in 180nm CMOS −Borkar, S., Karnik, T., Narenda, S., Tschanz, J., Keshavarzi, A., De, V. Parameter Variations and Impact on Circuits and Microarchitecture. In Proc. of DAC (2003), 338-342. 10

11. 11 Impact of Variation Die-to-die frequency variation 11

12. 12 Statistical Description  The combined set of underlying deterministic and random contributions are lumped into a combined “random” statistical description.

13. 13 Variation Parameter Parameters treated as Random Variables (RV) P i : a structural or electrical parameter e.g. −W, −tox, −Vth, −channel mobility, −coupling capacitances, −line resistances. Delay of each edge: a function of P i ’s  Delay: an RV too

14. Timing Graph Timing Graph:  G = {N, E, ns, nf } (directed)  ns: source node  nf: sink node  N: nodes  E: edges  d i : Edge weight: gate/interconnect delay Statistical timing graph:  A timing graph if ith edge weight d i is an RV. Critical path delay:  Changes from one die to another  is an RV SSTA must compute the characteristics of this RV  By computing its −PDF: probability-distribution function or −CDF: cumulative-distribution function 14

15. 15 SSTA Environmental uncertainty (supply, temperature):  Modeled by worst case margins Process uncertainty:  Modeled statistically

16. CDF and PDF t1 Prob. that the delay up to this (output) node is t1 t1 Area under f(t) from 0 to t1: Prob. that critical path delay is < t1 predicted 16

17. Normal Distribution Gaussian or Normal Distribution 17

18. Normal Distribution 18 [Sill05] 99.7% to be exact

19. New vs. Older Technology Increasing variation Probability Distribution Delay New Old 19

20. SSTA  Can compute µ and σ  CDF and PDF can be derived from one another Given:  CDF of circuit delay and  required performance constraint Can compute  anticipated yield Given  CDF of the circuit delay and  required yield Can compute  maximum frequency at which the set of yielding chips can be operated 20

21. SSTA SSTA problem definition:  path p i −a set of ordered edges from source to sink in G Di:Di: −path-length distribution of p i, computed as the sum of the weights d for all edges k on the path.  SSTA finds distribution of −D max = max(D 1,..., D i,..., D npaths ) among all paths Motivated from PERT in project management:  PERT: Project Evaluation and Review Technique 21

22. Sequential Paths  T path = t 0 +t 1 +t 2 +t 3 +…t (n-1) t i for n random variables:  t i = (µ,   Assume: independent delays Path delay RV:  T path = (n×µ,  × √n) … 22

23. Sequential Paths 3 sigma delay on path:  Statistical:n×µ  n  ×   Worst case:n×(µ   Overestimate n vs.  n … 23

24. Parallel Paths  T cycle = max(t p0, t p1,, t p(n-1) )  T 0 = Timing wall  P(T cycle <T 0 ) = P(t p0 <T 0 )×P(t p1 <T 0 )… = [P(t p <T 0 )] n −Assuming: probabilities are equal For 50% reliability (Yield > 50%):  0.5 = [P(t p <T 50 )] n  P(t p <T 50 ) = (0.5) (1/n) 24

25. Parallel Paths  P(t p <T 50 ) = (0.5) (1/n)  Too Many paths N=10 8  0.999999993 N=10 10  0.99999999993 For 50% yield, we need  6 to 7   T 50 =T mean +7  path 25

26. SSTA Challenges (*) Challenges:  Topological correlation  Spatial correlation  Non-normal process parameters and non-linear delay models  Skewness due to max operation 26

27. Topological Correlation (*) Reconvergent path  P 1 and P 2 share g 0 edge and reconverge at g 3 output node (r) 27

28. Topological Correlation (*) Topological correlation between the arrival times:  Input arrival times at the reconvergent node become dependent on each other  RVs are not independent  Complicates the max operation at the reconvergent node 28

29. Spatial Correlation (*)  For P 1 and P 3 (no edges shared) if gates g1 and g2 are close on the die,  Correlation between the two path delays  Affects both sum and max −With SC: −L eff, −Temperature −Supply voltage −No SC: −t ox, −N a 29

30. Correlation (*) Correlated Gate B delay Gate A delay Gate B delay Gate A delay Uncorrelated 30

31. Systematic (Correlated Random) WID Variation (*) Sample 1 Sample 2Sample 3 [Samaan, ICCAD 04] Models distance-dependent smooth variations Exact shape is unknown 31

32. Non-Normal Process Parameters (*) Gaussian distribution:  Most commonly observed distributions for RVs  A number of elegant results exist for them  Most of work for SSTA assumed normal dist. For −physical/electrical device parameters −gate delays −arrival times Problem:  Some physical device parameters may be significantly non-normal: −e.g. CD 32

33. Non-Normal Process Parameters (*) CD distribution:  Negative skewness (long tail in –ve direction) 33

34. Non-Linearity Non-linear dependence:  Even if some parameters are normal, dependence of electrical parameters (e.g. gate delays) on them may be non-linear −  Non-normal delays Assumption of initial work:  Linear dependence of gate delay on physical parameters −OK for small variations −Recent papers address this issue 34

35. Non-Normal Process Parameters Problems with non-normal:  Difficult modeling of an RV  Dependence between two non-normal RV cannot be expressed by a simple correlation factor 35

36. Skewness Due to Max Max operation is inherently non-linear  Max of two normal RVs is not normal −Typically positively skewed  Non-normal arrival time at one node is the input to max computation at down stream nodes  Need max operation of non-normal arrival times Most of the existing approaches assume normal arrival times 36

37. Skewness of Max  Error of non-normal is large when similar µ but very different σ −i.e. inputs of a gate have nominally balanced path delays but one path has a tighter delay distribution (e.g. passing from less number of gates)  For delay values < mean, A dominates  For delay values > mean, B dominates 37

38. Skewness of Max  Small skewness if similar µ and σ 38

39. Skewness of Max  If very different µ, the bigger dominates 39

40. References (*) [Blaauw08] Blaauw, Chopra, Srivastava, Scheffer, “Statistical Timing Analysis: From Basic Principles to State of the Art,” IEEE Transactions on CAD, Vol. 27, No. 4, April 2008. [Forzan09] Forzan, Pandini, “Statistical static timing analysis: A survey,” Integration, the VLSI journal, 42, 2009. [Sill05] F. Sill, “Statistical Static Timing Analysis and Statistical Static Timing Analysis and Modeling of Parameter Variations,” Lecture Slides, 2005 [Sinha07] D.Sinha,H.Zhou,N.V.Shenoy, “Advances in computation of the maximum of a set of Gaussian random variables,” IEEE Trans. Computer-Aided Design 26 (2007)1522–1533. 40

41. References [Agarwal03a] A. Agarwal, D. Blaauw, and V. Zolotov, “Statistical timing analysis for intra-die process variations with spatial correlations,” in Proc. ICCAD,2003, pp. 900–907. [Agarwal03b] A. Agarwal, V. Zolotov, and D. Blaauw, “Statistical timing analysis using Bounds and Selective Enumeration,” TCAD 2003, pp. 1243–1260. [Chang03] H. Chang and S. Sapatnekar, “Statistical timing analysis considering spatial correlations using a single PERT- like traversal,” in Proc. ICCAD, 2003, pp. 621–625. 41