1. Design, Simulation and synthesis of ADSL ATU-C Transport Class 4 Transmitter By Team 4 Winter Y2K for ELEN 603 at SCU

2. Objective n Study the IEEE ANSI T1.413 Standards. n Formulate the specifications of the project. n Create the VHDL Code. n Simulate individual components Test Bench. n Simulate, Analyze, synthesize and Report the overall system.

3. Input Data Channels AS0: Simplex Channel n 1.536 MBPS n DR = 48*8*4000 Ps n Goes to Interleaved. LS0: C-Channel n 16 KBPS n DR = 1/2*8*4000 n Goes to Interleaved. LS1: Duplex Channel n 160KBPS n DR=5*8*4000 PS n Goes to Fast Data Buf. n EOC (Embedded Operators Channel) not supported.

4. Frames n Interleaved Frame carries AS0 and LS0. n It requires Sync Byte, AEX and LEX bytes. n Fast Frame carries fast byte, 5 Bytes of LS1 and LEX Byte. n Super Frames contains 68 frames. n Last frame is the sync frame. n 0,1, 34 and 35 are filled with CRC and IBS.

5. ADSL Transmitter components n Mux/Sync n SuperFramer n Scrambler n CRC n FEC (not completed) n Interleaver

6. Mux/Sync n Multiplexed different Channels n Control flow of data through different modules n Synchronized clocks through the sub components

7. Scrambler n Achieve d.c balance? (is that correct?) n Avoid long sequence of “0”s and “1”s. n Make the data more random n Use polynomials to scramble

8. CRC (Cyclic redundancy codes) n Checks Validity of data and redundancy. n Use polynomials to add CRC bits. n Creates a CRC data for a superframe.

9. FEC (not done) n Add redundancy Check Bytes according to message and check polynomials. n This was not done because of lack of time and resources.

10. Interleaver n Spreads the bytes so that they experience independent errors. n Mix up various frames on the Interleave n The effect of the error is spread over the message so that it is possible to recover the data.

11. Simulation Results n Individual Test Benches were created. n Check and Verification. n Integration piece by piece. n Results. n Unexpected surprises.

12. Analysis & Conclusion n Used Exemplar Logic. n Not enough time to fully complete all components. n Inconsistencies and unexpected errors. n Able to Simulate and Verify the behavior of most components. n We learned a lot the very hard way.