1. Outline Motivation Simulation Framework Experimental methodology STT-RAM (Spin Torque Transference) ReRAM (Resistive RAM) PCRAM (Phase change) Comparison Summary

2. Motivation Up till now, sizing down the DRAM cell transistors  – more information density – higher speeds – less dollars per bit However, decreasing the cell size is becoming increasingly challenging and no viable solutions are known beyond 20nm (around year 2016) – scaling down transistors yield more leakage charge which lead to more refreshing power New memory technologies must be investigated: – In this project: STT-RAM, ReRAM and PCRAM

3. Lots of papers study the aforementioned technologies separately, but none study in depth the three under the same framework and with the same metrics In this work, we study the three NVMs with a novel system based simulator, NVSIM, and compare the three against each other and DRAM in terms of read/write latency, read/write power, area and leakage power Motivation

4. Simulation Framework NVSIM: System-based simulator based on CACTI for non- volatile memories: Flash, STT-RAM, ReRAM and PCRAM Two usage modes: – Given a memory architecture, NVSIM outputs read/write latency, read/write energy, area and leakage power – Given an optimization target amongst read/write latency, r/w energy, area and leakage power, NVSIM outputs the best chip organization that accomplish that optimization target: number of banks, subbanks, internal routing, etc. NVSIM has been evaluated against actual prototypes within a 30% of error

5. Area estimation – The size of the NMOS must be large enough so that it has the capability of driving the current needed to switch the state of the resistor (write operation) – Short write pulses induce large currents  larger transistors – The driving capability of the access transistor depends on the width- length ratio. Timing and power estimation. NVSIM… – …considers wire resistances and capacitances from interconnects, switching resistance, gate and drain capacitances, etc – …uses the most up-to-date transistors from ITRS – …is a system-level simulator, not a material simulator  it only models static behavior of storage elements Simulation Framework

6. Mode of usage – A *.cfg file deals with parameters such as data bus width, F in nm, chip capacity, chip organization (number of banks, routing, etc.) Optimization target: area, r/w energy and latency, leakage power – A *.cell file deals with parameters such as On/off resistances, transistor aspect ratio, etc. Simulation Framework

7. Experimental methodology In order to fill the *cfg and *cell files sensibly two aspects have been taken into account: – Baseline from actual prototypes published in the literature – Scaling rules from main manufactures and academia (ITRS) The three NVMs have been evaluated for four consecutive years: 2011, 2012, 2013 and 2014 – Each memory tech. is evaluated against the rest that are predicted to be contemporary (which doesn’t mean the same iso-process)

8. STT-RAM Very old technology, even before than CMOS Information is encoded as a magnetic field in a ferro-magnetic material Renewed interest thanks to the discovery of the Magnetic Tunnel Junction – In a ferromagnet, conduction electron spins are aligned up or down w.r.t the magnetic field.

9. Principles of operation: – Two layers are separated by a very thin insulator. – If the electron spins of the two layers are in the same alignment (parallel), more electrons are allowed to tunnel through the insulator  low resistive state – If the spins are in different alignment (anti-parallel), electrons are inhibited from tunneling through the insulator  high resistive state – “1”s and “0”s are encoded as parallel and anti-parallel configurations. – Read can be performed by injecting a current and sensing the voltage or inducing a voltage and sensing the current – Data writing is performed by using the spin-polarized current to change the magnetic orientation STT-RAM

10. STT-RAM cell: – On fixed layer and one free layer STT-RAM

11. ReRAM Based on a circuit element called “memristor”: Discovered by HP in 2008 the “memristance” at a particular time depends on the voltage applied to the memristor during the past to that time the memristor behaves like an ordinary resistance at any given instant in time, measured in ohms Multilevel cells: can store more than 2 logical values Still not very matured technology The largest memory achieve so far is 4Mbits

12. Thanks to wide gap between high and low resistive states, the memristor is amenable to build crossbar-like structures ReRAM

13. PCRAM Some materials change its resistivity when changing from crystalline(low R) and amorphous phase(high R) The material is deformed by applying a quick high amplitude current pulse that heats up the material to 660ºC To put it back to crystalline phase, it is warmed up to its crystallization temperature (around 350ºC) and annealed it back  this is possible thanks to the threshold switching

14. Data is read by applying a voltage and sensing the current or applying a current and sensing the voltage decay Typically, the access device is a MOS transistor, even though others are possible: BJT, diode, etc PCM can be engineered to store multiple bits per cell Commercial chips are available PCRAM

15. Scalability analysis: As cells become smaller it should be faster to warm up the PC material, specifically, if the cell is scaled by k then: Ron and Roff increases by k Programming voltage remains the same Programming current: 1/k (i.e decreases) Switching time: 1/k^2 PCRAM

16. Area NVMs offer the highest density beyond year 2013 Amongst all NVMs, PCM seems to be the densest, followed by ReRAM. There is no clear winner from year 2014. However, ReRAM is crossbar-friendly (no taken into account in the study)

17. Read Latency ReRAM is the fastest memory amongst NVMs. DRAM will remain faster in the upcoming years

18. ReRAM is the fastest memory amongst NVMs. PCM writes are the slowest  A lot of research effort is spent on new materials to speed up the write operation DRAM will remain faster in the upcoming years WriteLatency

19. All NVMs are much more energy efficient than DRAM! PCM is perhaps the most expensive by a small factor amongst NVMs Read Energy

20. PCM is the most expensive in term of write energy but from year 2013, PCM energy is lower than DRAM Clear advantages in terms of energy of NVMs against DRAM Write Energy

21. ReRAM the least leaky NVM NVMs, on avarage, less leaky than DRAM Leakage

22. Summary NVMs show clear advantages on power consumption over DRAM in the upcoming years In terms of information density, NVMs also win over DRAM thanks to the small cell size and multi-level logic capability Due to the non-volatility nature, NVMs do not need to be refreshed like DRAM NVMs are still slow in comparison to DRAM All the evaluated NVMs are CMOS compatible