1. Memory/Storage Architecture Lab 컴퓨터의 개념과 실습 Assembly Example

2. Memory/Storage Architecture Lab 22 Python vs. Assembly PythonAssembly f = (g + h) – (i + j) ADD R5, R1, R2 ADD R6, R3, R4 SUB R0, R5, R6 f is mapped to R0 g is mapped to R1 h is mapped to R2 i is mapped to R3 j is mapped to R4

3. Memory/Storage Architecture Lab 33 Python vs. Assembly PythonAssembly g = h + A[i] ADD R4, R2, R3 LDR R5, [R4] ADD R0, R1, R5 g is mapped to R0 h is mapped to R1 R2 contains the base address of array A[]. i is mapped to R3.

4. Memory/Storage Architecture Lab 44 Python vs. Assembly PythonAssembly if (i == j): f = g + h else: f = g – h CMP R3, R4 BNE ELSE ADD R0, R1, R2 B EXIT ELSE: SUB R0, R1, R2 EXIT: f is mapped to R0 g is mapped to R1 h is mapped to R2 i is mapped to R3 j is mapped to R4

5. Memory/Storage Architecture Lab 55 Python vs. Assembly PythonAssembly while (save[i] == k): i = i + j LOOP: ADD R4, R0, R3 LDR R5, [R4] CMP R2, R5 BNE EXIT ADD R0, R0, R1 B LOOP EXIT: i is mapped to R0 j is mapped to R1 k is mapped to R2 R3 contains the base address of array save[].

6. Memory/Storage Architecture Lab 66 Example Assembly Code & ISA sum = 0 list = [11, 13, 16] for i in range(0,3): sum = sum + list[i] sum = 0 list = [11, 13, 16] for i in range(0,3): sum = sum + list[i] MOV R0, #0 MOV R2, #6 L: ADD R2, R2, #1 LDR R1, [R2] ADD R0, R0, R1 CMP R2, #9 BNE L MOV R2, #10 STR R0, [R2] MOV R0, #0 MOV R2, #6 L: ADD R2, R2, #1 LDR R1, [R2] ADD R0, R0, R1 CMP R2, #9 BNE L MOV R2, #10 STR R0, [R2] 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF PC0 PSR0 R032 R143 R25 R313 R42 R57 R699 R78 RegisterMemory

7. Memory/Storage Architecture Lab 77 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory MOV R0, #0 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC0 PSR0 R032 R143 R25 R313 R42 R57 R699 R78 PC1 PSR0 R00 R143 R25 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

8. Memory/Storage Architecture Lab 88 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory MOV R2, #6 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC1 PSR0 R00 R143 R25 R313 R42 R57 R699 R78 PC2 PSR0 R00 R143 R26 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

9. Memory/Storage Architecture Lab 99 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory ADD R2, R2, #1 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC2 PSR0 R00 R143 R26 R313 R42 R57 R699 R78 PC3 PSR0 R00 R143 R27 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

10. Memory/Storage Architecture Lab 10 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory LDR R1, [R2] Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC3 PSR0 R00 R143 R27 R313 R42 R57 R699 R78 PC4 PSR0 R00 R111 R27 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

11. Memory/Storage Architecture Lab 11 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory ADD R0, R0, R1 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC4 PSR0 R00 R111 R27 R313 R42 R57 R699 R78 PC5 PSR0 R011 R111 R27 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

12. Memory/Storage Architecture Lab 12 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory CMP R2, #9 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC5 PSR0 R011 R111 R27 R313 R42 R57 R699 R78 PC6 PSR0x8000 R011 R111 R27 R313 R42 R57 R699 R78 31302928 1000… NZCV 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

13. Memory/Storage Architecture Lab 13 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory BNE L Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC6 PSR0x8000 R011 R111 R27 R313 R42 R57 R699 R78 PC2 PSR0x8000 R011 R111 R27 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

14. Memory/Storage Architecture Lab 14 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory ADD R2, R2, #1 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC2 PSR0x8000 R011 R111 R27 R313 R42 R57 R699 R78 PC3 PSR0x8000 R011 R111 R28 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

15. Memory/Storage Architecture Lab 15 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory LDR R1, [R2] Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC3 PSR0x8000 R011 R111 R28 R313 R42 R57 R699 R78 PC4 PSR0x8000 R011 R113 R28 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

16. Memory/Storage Architecture Lab 16 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory ADD R0, R0, R1 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC4 PSR0x8000 R011 R113 R28 R313 R42 R57 R699 R78 PC5 PSR0x8000 R024 R113 R28 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

17. Memory/Storage Architecture Lab 17 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory CMP R2, #9 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC5 PSR0x8000 R024 R113 R28 R313 R42 R57 R699 R78 PC6 PSR0x8000 R024 R113 R28 R313 R42 R57 R699 R78 31302928 1000… NZCV 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

18. Memory/Storage Architecture Lab 18 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory BNE L Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC6 PSR0x8000 R024 R113 R28 R313 R42 R57 R699 R78 PC2 PSR0x8000 R024 R113 R28 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

19. Memory/Storage Architecture Lab 19 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory ADD R2, R2, #1 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC2 PSR0x8000 R024 R113 R28 R313 R42 R57 R699 R78 PC3 PSR0x8000 R024 R113 R29 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

20. Memory/Storage Architecture Lab 20 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory LDR R1, [R2] Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC3 PSR0x8000 R024 R113 R29 R313 R42 R57 R699 R78 PC4 PSR0x8000 R024 R116 R29 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

21. Memory/Storage Architecture Lab 21 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory ADD R0, R0, R1 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC4 PSR0x8000 R024 R116 R29 R313 R42 R57 R699 R78 PC5 PSR0x8000 R040 R116 R29 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

22. Memory/Storage Architecture Lab 22 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory CMP R2, #9 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB PC5 PSR0x8000 R040 R116 R29 R313 R42 R57 R699 R78 PC6 PSR0x4000 R040 R116 R29 R313 R42 R57 R699 R78 31302928 0100… NZCV 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF

23. Memory/Storage Architecture Lab 23 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory BNE L Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF PC6 PSR0x4000 R040 R116 R29 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF PC7 PSR0x4000 R040 R116 R29 R313 R42 R57 R699 R78

24. Memory/Storage Architecture Lab 24 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory MOV R2, #10 Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF PC7 PSR0x4000 R040 R116 R29 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF PC8 PSR0x4000 R040 R116 R210 R313 R42 R57 R699 R78

25. Memory/Storage Architecture Lab 25 Instruction Set Architecture RegisterMemory Before Register and Memory After Register and Memory RegisterMemory STR R0, [R2] Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB Assumptions  32 bit ISA  # of registers = 8 + PC (Program Counter) + PSR (Program Status Register)  Memory size = 176KB 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 100 0xAFFF PC8 PSR0x4000 R040 R116 R210 R313 R42 R57 R699 R78 0x8000 MOV R0, #0 1 MOV R2, #6 2 L: ADD R2, R2, #1 3 LDR R1, [R2] 4 ADD R0, R0, R1 5 CMP R2, #9 6 BNE L 7 MOV R2, #10 8 STR R0, [R2] 0x80FF 0xA000 711 813 916 1040 0xAFFF PC9 PSR0x4000 R040 R116 R210 R313 R42 R57 R699 R78