1. Analytical Approach for Soft Error Rate Estimation of SRAM-Based FPGAs Ghazanfar (Hossein) Asadi and Mehdi B. Tahoori Why Soft Error Rate (SER) Estimation? Exponential growth of vulnerable bits due to Moore’s law High cost of Error tolerant schemes To make appropriate cost/reliability trade-offs » Where to put redundancy Why an analytical method? Previous work: Fault Injection » Time-consuming / Incomplete / Expensive » Needs physical prototype board » Cannot be used in design phases Northeastern U N I V E R S I T Y Electrical and Computer Engr. Department Error Definitions Soft Errors: » Intermittent malfunctions of the hardware » Not reproducible Energetic Particles  Single Event Upsets (SEUs)  Soft Errors  (may cause) System Failure Error Models in FPGAs Memory resources: » User bits  Transient errors » Configuration bits  Permanent errors Error Models in FPGAs SER Estimation in Synchronous Circuits Traversing structural paths [Asadi04] » From error sites to outputs SER Estimation in ASIC Designs S(n): System failure probability (SFP) vector » S i : SFP given node i erroneous » n: total error sites Experiments on ISCAS89 show that: » Three order of magnitude faster » Compared to random-input simulation » Accuracy: more than 90% FPGA vs. ASIC in SER Estimation ASIC: transient error » Only requires propagation probability FPGA: both transient & permanent errors » Transient errors: the same » Permanent errors: needs activation as well No attenuation in FPGAs during error propagation Nodes with different error rates in FPGAs » Error sites: all nodes (even routing signals) SER Estimation of FPGAs Compute permanent error rates for all nodes » PR i : permanent error rate of node i » n: total number of fault sites Compute netlist failure probability vector » N i = failure prob. given node i erroneous Open & stuck-at errors: » N i = [SP i  PP i (0) + (1-SP i )  PP i (1)] = PP i » PP i : Propagation prob. (the method used for ASIC) Bridging wired-AND & wired-OR errors (nets i and j): » N i (w and )=[SP i  (1-SP j )  PP i (0)] + [(1-SP i )  SP j  PP j (0)] » N i (w or )=[SP i  (1-SP j )  PP j (1)] + [(1-SP i )  SP j  PP i (1)] LUT bit-flip: » N i = Activation Prob. (cell)  Prop. Prop. (LUT output) CircuitS27S298S344S349s382s386 Routing64459536650807714 LUT68418392520712660 Control/ Clocking 40140168187207160 Total17210171096135717261534 Number of sensitive SRAM bits for each part (Results in terms of cycles) CircuitS27S298S344S349s382s386 Routing2.072.862.582.913.303.82 LUT14.4920.7517.3320.4822.0830.07 Control/ Clocking 1.181.311.361.40 1.77 Mean Time To Manifest errors to outputs CircuitS27S298S344S349s382s386 SFR (FIT)1.719.879.9912.7716.0412.11 SP Time (sec)0.150.760.911.091.251.05 SFR Time (sec)0.020.090.130.140.190.25 Total Time (sec)0.170.851.041.231.441.30 FIT rate per bit: 0.01 Number of Clock cycles: 1000 SP Time: Signal Probability computation time SFR Time: System Failure Rate computation time Platform: Sun Solaris Ultra-10 » Equipped with 256 MB main memory System Failure Rate & Estimation Time Transient errors » User flip-flops » Logic gates » Block RAMs Permanent errors » Routing: MUX select bits PIP: Short/Open Buffer: On/Off » LUT » Control/Clocking Bits System failure rate vector (S) = PR  N » S i = PR i  N i System Failure Rate (SFR) » For the first clock: » For c clock cycles » c clock cycles after particle hit Summary & Conclusions A new method for extracting dependability parameters » For SRAM-based FPGAs No physical implementation required » Can be used in early design stages Very fast simulation time Can cover all possible faults Mean Time To Manifest (MTTM) errors to outputs: » MTTM(Control/clocking) < MTTM(routing) << MTTM(LUT) Future Work Extending our method to include all error models Experimental Results