1. Agenda MODERN WP3 Meeting November 9 Catania, Italy Version: 0.2 WP3: Wilmar Heuvelman T3.1 Michel BerkelaarT3.2 Igor Loi T3.3 Massimo PoncinoT3.4 Rick Janssen

2. CONFIDENTIAL 2 MODERN General Meetings Catania, Nov. 9 & 10, 2010 Contents Objectives for WP3 meeting Timeline Matrix Application overview per task Gantt chart

3. CONFIDENTIAL Objectives Opportunity to exchange results between partners, discussions Reply on the feedback of the reviewers –Identify key achievements/deliverables –Identify links between other WP’s/Task –Identify links to demonstrators (WP5) Time line and planning –Deliverables & Milestones –Organisation Matrix (Afternoon) Gantt Chart (afternoon) Summary for WP3 presentation in General meeting (10/11) 3 MODERN General Meetings Catania, Nov. 9 & 10, 2010

4. CONFIDENTIAL Timeline(1) Review & Deliverables Next review: March 1 2011-> deliverables 2010! 4 th half year progress report-> end Feb 2011 Deliverables (all M24, end Feb 2011): 4 MODERN General Meetings Catania, Nov. 9 & 10, 2010

5. CONFIDENTIAL Timeline(2) Milestones 5 MODERN General Meetings Catania, Nov. 9 & 10, 2010

6. CONFIDENTIAL 6 MODERN General Meetings Catania, Nov. 9 & 10, 2010 Matrix Application overview per task and partner 6 MODERN General Meetings Catania, Nov. 9 & 10, 2010 TasksCircuit ModelsMethods Tools&Flows PV aware Circuits EMI/EMC Application3.13.23.33.4 DigitalNXP,STI,TUD,TUE, UNRM,LIRM UNBO,NXP,STI, UNCA, UNGL,UNRM POLI,LETI,UPCSTI,LIRM AMSSTI,UNRMNMX,STI,UNRMIFX,UPCNXP,STI RFNXP,STIIFXNXP NVMNMX

7. CONFIDENTIAL T3.1 Application overview Alternative to SSTA: RDE based TL gate simulation (TUD) Cell level HDL models(UNRM,ST) SSTA based on moment propagation Surrogate behavourial models(UNRM,ST) Model Order Reduction (MOR) 7 MODERN General Meetings Catania, Nov. 9 & 10, 2010 7 MODERN General Meetings Catania, Nov. 9 & 10, 2010 TasksCircuit Models Application3.1 DigitalNXP,STI,TUD, TUE,UNRM,LI RM AMSSTI,UNRM,NX P RFNXP,STI NVM

8. CONFIDENTIAL T3.1 Application overview Application DigitalAMSRFNVM Partner NXP,STI,TUD,TUE,U NRM,LIRM STI,UNRM,NXP NXP,STI Activity Alternative to SSTA: RDE based TL gate simulation (TUD) Cell level HDL models(UNRM,ST) SSTA based on moment propagation(LIRM) Model Order Reduction (MOR) Surrogate behavourial models(UNRM,ST) 8 MODERN General Meetings Catania, Nov. 9 & 10, 2010

9. CONFIDENTIAL 9  First European Workshop on CMOS Variability  Need to meet industry and academia  Organized by LIRMM (Nadine Azemard)  Help of University of Glasgow, UK  Help of CEA-Leti, STMicroelectronics (Grenoble, Fr)  50 participants  Different countries  Selected papers included in a special issue of The Journal of Low Power Electronics (JOLPE).

10. CONFIDENTIAL T3.2 Application overview ABB & algorithms for FBB allocation (UNBO) Influence of PV on speed and energy on logic (UNCA) Circuit design optimization (UNRM,STI) Activity analysis tool(NXP) Spice like simulation on sensing memory circuit (NMX,UNGL) Upgrade on statistical circuit simulator (UNGL) 10 MODERN General Meetings Catania, Nov. 9 & 10, 2010 10 MODERN General Meetings Catania, Nov. 9 & 10, 2010 TasksMethods Tools&Flows Application3.2 DigitalUNBO,NXP,STI, UNCA, UNGL,UNRM AMSNMX,STI,UNRM RF NVMNMX

11. CONFIDENTIAL T3.3 Application obverview Variablity assesment (IFX) M&C for digital (POLI,LETI,UPC,STI) and analog(IFX,UPC) Tolerant redundant logic (UPC) Modular power gating (POLI) Regular cells (UPC) 11 MODERN General Meetings Catania, Nov. 9 & 10, 2010 11 MODERN General Meetings Catania, Nov. 9 & 10, 2010 TasksPV aware Circuits Application3.3 DigitalPOLI,LETI,UPC AMSIFX,UPC RFIFX NVM

12. CONFIDENTIAL Task T3.3: Partner Participation in subtasks AMS & RF DigitalDelivs 3.3.1 Variability Assessment IFATD3.3.2 3.3.2 M&C Strategies IFAT UPC POLI UPC LETI ST D3.3.2 3.3.3 PV-aware Circuit-level design UPC ST? D3.3.2 D3.3.3

13. CONFIDENTIAL T3.3 Partner Interaction and exchange POLIIFATUPCCEAST POLI -- New Cell Libraries PV Monitors Tech libraries IFAT - Exchange info on PV monitors? --- UPC Sleep cell Exchange info on PV monitors - PV monitors (for WP4) Tech libraries CEA - PV monitors - Tech libraries ST ---- (Partner in a row might need from partners in a column)

14. CONFIDENTIAL T3.4 Application overview Power distribution model for chip- package-PCB (STI) Clock tree synthesis for low EMI (STI) Substrate noise (NXP) Mutual interaction for RF-power devices (NXP) 14 MODERN General Meetings Catania, Nov. 9 & 10, 2010 14 MODERN General Meetings Catania, Nov. 9 & 10, 2010 TasksEMI/EMC Application3.4 DigitalSTI,LIRM AMSNXP,STI RFNXP NVM

15. CONFIDENTIAL Gantt chart Technical Annex 15 MODERN General Meetings Catania, Nov. 9 & 10, 2010

16. CONFIDENTIAL Gantt chart (proposed) 16 MODERN General Meetings Catania, Nov. 9 & 10, 2010 PlannedActual Pre- requisit es Mile-stone Show Gantt chart for: Planned Highlight month:21 KEY:Planned DurationPlanned % FinishedActual DurationActual % Finished Goals % ##### 1/102/103/104/105/106/107/108/109/10##### 1/112/113/114/115/116/117/118/119/11##### 1/122/12 Star t Dur atio n Star t Dura tion Done 123456789101112131415161718192021222324252627282930313233343536 D3.1.1NXP, ST-I1, TUD, TUE, UNRM1, UNIRM2 Set of alternative symbolic models for lib cells1111 100%-M3.1 BLUE TRUEFALSE D3.1.2LIRM, NXP, ST-I, TUD, TUE, UNRM Statistical methodology for characterisation of digital and AMS&RF circuits131113 50%D3.1.1M3.2 111111111111BLUE TRUE FALSE D3.1.3NXP, STI, TUD, TUE, UNRM Automated and validated characterisation flow for lib cells, and AMS&RF blocks2536 0%D3.1.2- 111111111111111111111111TRUE D3.2.1ST-I1, UNBO, UNCA, UNRM1 Process development kit (PDK), circuit techniques, and speed-up algorithms for PV-aware circuit simulation1111 100%-M3.3 BLUE FALSE D3.2.2NMX, NXP, UNBO, UNCA, UNGL, UNRM Standardized PV-aware tools for simulation of digital blocks, AMS&RF blocks, and NVM arrays131113 50%D3.2.1M3.4 111111111111BLUE TRUE FALSE D3.2.3NMX, UNBO, UNRM Integration and validation of high-speed PV- aware simulation tools for digital blocks, AMS&RF blocks, and NVM arrays2536 0%D3.2.2- 111111111111111111111111TRUE D3.3.1IFXA, LETI, POLI, UPC PV-tolerant schematics evaluation and Monitor & Control (M&C) strategies in digital and AMS&RF1111 100% M3.5 BLUE FALSE D3.3.2IFXA, LETI, POLI, UPC PV-tolerant lib cell designs and M&C implementation in digital and AMS&RF131113 50% M3.6 111111111111BLUE TRUE FALSE D3.3.3IFXA, UPC, POLI Synthesis and simulation of digital blocks, and measurement and verification of critical AMS&RF2536 0% 111111111111111111111111TRUE D3.4.1LIRM, ST-I2 Impact of supply noise, and clock distribution on EMI and circuit timing1111 100% BLUE FALSE D3.4.2NXP RF-interaction models for combined PCB- package-IC1111 100% M3.7 BLUE FALSE D3.4.3NXP, ST-I Substrate RF coupling, RF co-simulator, Power Distribution Model (PDN) evaluation and analysis flow for combined IC-package-PCB1311 50% D3.4.2; D5.2.1M3.8 111111111111BLUE TRUE FALSE D3.4.4ST-I Implementation and evaluation of clock tree synthesis techniques for low EMI1311 50%D3.4.1M3.9 111111111111BLUE TRUE FALSE D3.4.5NXP Design flow for RF co-habitation2511 D3.4.3- 111111111111111111111111TRUE D3.4.6NXP Measurements of substrate noise monitor2511 D3.4.3; D5.2.2- 111111111111111111111111TRUE D3.4.7ST-I Design solutions for EMI-aware design for automotive, and EMI evaluation of combined IC- package-PCB2511 D3.4.4- 111111111111111111111111TRUE

17. CONFIDENTIAL Links to WP’s /Tasks T3.1 Model Order Reduction(NXP) to T5.3(input) T3.1 & T3.2(input) Trial PDK (STI,UNRM) to 5.3 T3.1 to WP2 (input)? T3.2 to T5.1(input) and T2.3(input): char data used for checks(NMX) –Input not necissarily but would be beneficial T3.3 AMS M&C to T5.2(input) (IFX) –Test structrures –M&C T3.3(input) fault detectors (LETI) T5.2 T3.4 to T5.2(input): substrate noise (NXP) T3.4 to T3.1(input): MOR (NXP) T3.4(input M12) to T4.2(input M24): low EMI arch (STI) 17 MODERN General Meetings Catania, Nov. 9 & 10, 2010

18. CONFIDENTIAL 18 MODERN General Meetings Catania, Nov. 9 & 10, 2010