1. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.1. Light switch example.

5. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.5. Minimization using Karnaugh maps.

6. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.6. Four-variable Karnaugh maps illustrating don’t cares.

12. Figure A.12. A transistor circuit implementation of a NOR gate.

14. (a) NMOS transistor (b) PMOS transistor

15. Figure A.15. CMOS realization of a NOT gate. (b) Truth table and transistor states

17. (a) Circuit (b) Truth table and transistor states Figure A.17. CMOS realization of a NAND gate. (b) Truth table and transistor states

18. Figure A.18. CMOS realization of a NOR gate. (b) Truth table and transistor states (a) Circuit

19. Figure A.19. CMOS realization of an AND gate.

20. Figure A.20. The voltage transfer characteristic for the CMOS inverter. V f V x 0V V supply V t  V t  +V supply Slope1  = V t

21. Propagation delay Transition time T V 1 V 1 V 0 V 0 90% 50% 10% 90% 50% 10% Input waveform Output waveform Figure A.21. Definition of propagation delay and transition time.

22. (b) Equivalent circuit (c) Truth table xf e (a) Symbol 0 0 1 1 0 1 0 1 Z Z 0 1 f ex x f e = 0 e = 1 xf f x e (d) Implementation Figure A.22. Tri-state buffer.

23. Figure A23. A 14-pin integrated circuit package (DIP).

25. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.25. Gated SR latch.

27. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.27. Gated D latch.

28. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.28. Master-slave D flip-flop.

29. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.29. A negative edge-triggered D flip-flop.

30. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.30. T flip-flop.

32. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.32. Master slave D flip-flop with Preset and Clear.

33. DQ Q Figure A.33. A simple shift register. Clock DQ Q DQ Q DQ Q InOut F 1 F 2 F 3 F 4

37. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.37. A BCD to seven-segment display decoder.

38. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.38. A four-input multiplexer.

40.    

42. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.42. A simplified sketch of the PLA in Figure A.41.

45.     PAL-like Figure A.45. Structure of a complex programmable logic device (CPLD).

47. x0=z0=  x0=z0=  x0=z0=  x1=z0=  x1=z1=  x1=z0=  x1=z0=  x0=z1=  S2S3 Figure A.47. State diagram of a mod-4 up/down counter that detects the count of 2. S1 S0S0

53. / / / / / / / / / / / /

59. TABLEA.1Two3-variablefunctions x 1 x 2 x 3 f 1 f 2 00011 00111 01001 01110 10001 10101 11000 11110

60. TABLEA.2Evaluationoftheexpressionx 1 x 2 + x 2 x 3 x 1 x 2 x 3 x 1 x 2 x 2 x 3 x 1 x 2 + x 2 x 3 =f 1 000101 001101 010000 011011 100000 101000 110000 111011

61. TABLEA.3Truth-table technique for proving equivalence of expressions Left-handsideRight-handside wyzy+zw(y + z)wywzwy + wz 00000000 00110000 01010000 01110000 10000000 10111011 11011101 11111111

62. TABLEA.4Rulesofbinarylogic NameAlgebraicidentity Commutativew + y=y + wwy=yw Associative(w + y) + z=w + (y + z)(wy)z=w(yz) Distributivew + yz=(w + y)(w + z)w(y + z)=wy + wz Idempotentw + w=www=w Involutionw=w Complementw + w=1ww=0 deMorganw + y=wywy=w + y 1 + w=10w=0 0 + w=w1w=w  

63. Please see “portrait orientation” PowerPoint file for Appendix A Figure PA.2.