2. Device Interface Board for Wireless LAN Testing Team May 06-15 Client ECpE Department Faculty Advisor Dr. Weber Team Members Matthew Dahms – EE Justine Skibbe – EE Joseph Chongo – EE April 26, 2006

3. Presentation Outline Project Overview  Introduction  Problem Statement  Operating Environment  Intended Users & Uses  Assumptions and Limitations  End-Product Description Project Activities  Previous Accomplishments  Technology Considerations  Present Accomplishments  Planned Activities Resources & Schedule  Estimated Resources  Schedules Closure Materials  Additional Work  Lessons Learned  Risk & Management  Closing Summary Figure 1: Teradyne Lab Entrance

4. Definitions ASK modulation – Amplitude shift keying. In this modulation scheme the amplitude is varied to indicate logic 0’s and 1’s DUT – Device under test (positive edge D flip-flop) ESD – Electrostatic discharge FPGA – Field programmable gate array. Used to test the DUT after receiving signals from the Teradyne tester Header – Preamble bits sent prior to the sending of information in a data packet time 1 0 1 0 D3 D2 D1 D0 Data Packet Header voltage Figure 2: Data Packet and Header

5. Definitions (cont.) NRZ – Non-return to zero. Using NRZ, a logic 1 bit is sent as a high value and a logic 0 bit is sent as a low value. PLL – Phase-locked loop RZ – Return to zero. This is the opposite of NRZ data. The signal state is determined by the voltage during the first half of each data binary digit. The signal returns to a resting state (called zero) during the second half of each bit. S/R Network – Send/Receive network. A combination of transmitters and receivers. Teradyne Integra J750 – Tester donated to Iowa State University by Teradyne. It is used in the testing of printed circuit boards and integrated circuits.

6. Project Overview

7. Acknowledgement Dr. Weber Nathaniel Gibbs Jason Boyd Rob Stolpman

8. Project Overview Problem Statement  In Fall 2004, ISU’s ECE Department introduced a senior design project with the goal of developing a wireless interface capable of receiving test signals and transmitting results to the department’s Teradyne Integra J750 tester.  For this project, the goal is to modify the current setup so that the wireless interface shall be capable of recovering a clock signal transmitted by the Teradyne system. Figure 3: Teradyne Integra J750

9. Project Overview Operating Environment  Operates in a controlled laboratory where the temperature range is 27°C to 33°C  Should be protected from ESD

10. Project Overview Intended Users  The user has knowledge in electrical and/or computer engineering.  The user has previous experience testing circuits with the Teradyne J750.  The user is familiar with Verilog programming language. Intended Uses  Functional test of a digital device via wireless interface  (Future) Wireless chipset test

11. Project Overview Assumptions  A sufficient clock-training signal can be sent by the Teradyne J750 over the S/R network to initialize the clock recovering circuitry.  The clock recovering circuit will be able to interact with the existing FPGA.  The current wireless communication network can transmit up to five feet. This assumption is based on the May05 team’s documentation.  The phase difference between the system clock of the Teradyne J750 and the recovered clock at the wireless interface will not be greater than the overall system clock frequency.

12. Project Overview Limitations  The Teradyne J750 is sensitive to temperature fluctuations and must operate within the calibrated temperature range.  To avoid the loss of data, the maximum rate at which user can send data is at 115.2 Kbps.  The existing transmitter and receiver communicate at 916.5 MHz. Therefore, nearby wireless signals at similar frequencies may disrupt the setup.  The communication link shall be limited to one frequency.  Limited to using only one FPGA. Using two FPGA’s, it would be possible to encode/decode the clock and test data into a single data stream. Figure 4: Temperature Requirements

13. Project Overview End-Product and Other Deliverables  Wireless interface with clock recovering circuit  Demonstration of wireless test  Update the manual for wireless test operation Figure 5: Cover page of wireless manual

14. Project Activities

15. Parallel-Serial Conversion  Needed to convert parallel data into serial data for transmission over the S/R network  Chose to use a shift register Figure 6: Shift Register attached to daughterboard Project Activities – Previous

16. Transmitters and Receivers TRM1 TRM2 RCV1 RCV2 Figure 7: Tx/Rx PCBs Project Activities – Previous

17. FPGA  Used to recognize header signal  Identifies test data  Presents test data to DUT  Presents reply to S/R network Figure 8: FPGA Project Activities – Previous

18. Figure 9: Final System Setup

19. Project Activities – Present Present Accomplishments Hardware Previous team’s project setup and tested PLL tested NRZ/RZ converter tested PCB milled & soldered Software Prototype control software for FPGA written IG-XL test template written

20. Project Activities – Definition Definition Activities  Initially wanted to test wireless chipset  May 05-29: Redefined project as “proof-of- concept” that J750 can wirelessly test a device  May 06-15: Incorporate clock recovering circuit and the DUT onto a PCB

21. Project Activities – Research Research Activities  Clock recovery What is it? How to implement it?  Teradyne How do IG-XL templates work? How to send data?

22. Project Activities – Approach Approach Considered & Used  Technology Considerations Clock recovery  Manchester encoding  PLL & NRZ/RZ converter combination Software  VHDL  Verilog

23. Project Activities – Approach Original SignalValue Sent Logic 00 to 1 (upward transition at bit centre) Logic 11 to 0 (downward transition at bit centre) The waveform for a Manchester encoded bit stream carrying the sequence of bits 110100 Manchester Encoding Figure 11: Graphical representation of Manchester encoding

24. Manchester Encoding  Advantages Very easy to implement Clock phase and frequency are both present  Disadvantages Too fast for current transmitters and receivers! Project Activities – Approach

25. PLL & NRZ/RZ converter combination  Advantages Don’t have to build new transmitters and receivers  Disadvantages PLL Must be “trained” Test data must follow a training signal NRZ/RZ converter needed

26. Project Activities – Approach Figure 10: Phase locked loop transient response a) Output of PLL when locked onto input of PLL b) PLL losing lock when no input is present

27. Project Activities – Approach Software  VHDL Advantages  Able to handle abstract levels of logic  More powerful than Verilog Disadvantages  This team has no experience using VHDL  Verilog Advantages  More intuitive  Previous team’s code was based on Verilog Disadvantages  No libraries for use in high-level constructs

28. Project Activities – Approach Hardware chosen - PLL & NRZ/RZ converter combination Language chosen - Verilog

29. Project Activities – Design Figure 12: Internal Components of a PLL

30. Project Activities – Design Phase Detector  Type I – XOR  *Type II – Generates lead or lag pulses Voltage Controlled Oscillator (VCO)  Centered at 115.2 KHz  Frequencies too far off of center frequency will not lock

31. Project Activities – Design NRZ/RZ Converter: Monostable Multivibrators  Chosen to convert NRZ data to RZ data  Must use an external RC combination to specify pulse widths

32. Project Activities – Design Figure 14: NRZ to RZ converter circuit with I/O waveforms

33. Project Activities – Design System Block Diagram Figure 10: Proposed final setup block diagram

34. Project Activities – Implementation Implementation Activities  Created clock recovering circuit on breadboard  Created PCB layout for final end-product  Created IG-XL test template Completed PCB Breadboard implementation of NRZ/RZ converter, PLL, & DUT

35. Problems encountered  Pin mapping FPGA grounding problem Errors uploading program to FPGA  Parasitics using breadboard setup Leads on capacitors Crosstalking Project Activities – Implementation

36. Project Activities – Testing Plan of attack Test components individually w/ function generator & oscilloscope Simulate code Test components individually on breadboard w/ J750 Test PCB components  Test code w/ J750  Test integrated system

37. Project Activities - Testing FPGA Code Works well in simulation:  Able to recognize header  Able to isolate PLL  Able to send data to DUT  Able to reset for additional sets of test data In practice: Some features of Verilog cannot be implemented by an FPGA. In addition to this, the same register may not be used in multiple “always” block statements.

38. Resources & Schedule

39. Schedule  Actual  Original  Revised

40. Schedule (cont.)  Actual  Original  Revised

41. Personnel Effort (as of April 26) Personnel Time Commitment *Completed hours ** Left on Co-op PersonnelProblem Definition Technology Considerations and Selection End- Product Design End-Product Prototype Implementation End- Product Testing End-Product Documentation End-Product Demonstration Project Reportin Total Matt Dahms9153340168742170 Joe Chongo10265085200226219 Srisarath Patneedi 810420* 10*70* Justine Skibbe 101139471451628170 Total3762164172501325106629

42. Previous Team Resources

43. Financial Resources (w/ labor) ItemW/O LaborWith Labor Parts and Materials: a. Printing of project posterDonated b. Teradyne Integra J750 Test SystemDonated c. Clock Recovery Chips (2)$3.86 d. Dual Monostable Multivib$0.53 e. Supplementary (Res, Cap, etc.) (D)$10.00 f. Voltage Regulators (D)$2.26 g. ZIF w/DIP to SOIC Converter (D)$38.60 h. SOIC CMOS Arrays (2) (D)$1.00 i. SOIC Schmitt Trigger (D)$0.37 j. SOIC PLL (D)$1.93 Labor at $12.00 per hour: a. Matthew Dahms$2,040 b. Joseph Chongo$2.628 c. Srisarath Patneedi$840 d. Justine Skibbe$2,040 Subtotal$7,548 Total$58.55$7,606.55

44. Closure Materials

45. Closure Materials – Project Evaluation MilestoneCurrent Progress (%) Scheduled Progress (%) Evaluated Status Evaluation Score (%) WeightTotal Project Definition100 Exceeded Criteria 10016 Technology Selection & Usage 100 Exceeded Criteria 10012 End-Product Design100 Exceeded Criteria 10015 End-Product Implementation 75100Partially Met Criteria 80108 End-Product Testing85100Partially Met Criteria 801512 End-Product Documentation (Manual) 90100Partially Met Criteria 80108 End-Product Demonstration 40100Did Not Meet Criteria 50126 Project Reporting (Deliverables) 100 Exceeded Criteria 10010 Total10087

46. Closure Materials - Commercialization Unlikely  Low Speed  Immobile  Inflexible  Cost Inefficient

47. Closure Materials - Additional Work Consider building faster TX/RX Consider using Manchester encoder/decoder Allow for more advanced DUTs

48. Closure Materials - Lessons Learned Circuit debugging techniques FPGA implementation Verilog Timing considerations Clock recovery Circuit board layout

49. Closure Materials - Lessons Learned What went well?  Teamwork  Record keeping  PCB What did not go well?  Damaging parts  Inefficient trouble shooting  FPGA implementations

50. Closure Materials – Risk Management Risk: Losing Team Member  Management: All members keep detailed & organized notes Risk: Loss of Data  Management: All data will be backed up using team gmail account Risk: Parts Malfunction  Management: Meticulous care in ESD procedures (using ESD bands)

51. Closing Materials Closing Summary  Problem – Integrate clock recovery circuitry into current system  Solution Use PLL for clock recovery Modify FPGA program to incorporate new components

52. Questions? Questions???

53. Thank You