1. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics VHDL register-transfer modeling: –basics using traffic light controller; –synthesis.

2. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL Combines a general-purpose programming language and an HDL. –Modeled on Ada programming language. VHDL is a rich language: –modules; –abstract data types. VHDL is case-insensitive.

3. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Abstract data types package lights is ---this is a comment subtype light is bit_vector(0 to 1); constant red : light : B”00”; constant green : light : B”01”; constant yellow : light : B”10”; end lights;

4. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL entities An entity defines the interface to the module. May plug various descriptions into the entity interface: –behavioral; –RT; –gate.

5. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL constants Bit constant: –‘0’, ‘1’ Bit vector constant: –B”0101”

6. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Traffic light entity declaration entity tlc_fsm is port( CLOCK: in BIT; -- machine clock reset : in BIT; -- global reset cars : in BIT; -- car signal short, long : in BIT; highway_light : out light := green; farm_light : out light := red; start_timer : out BIT );

7. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL processes A process is a unit of parallel execution. –All processes in an entity execute in parallel. Processes are used to build up behavior. Our RT model will have at least two processes: –combinational process for the logic; –sequential process for the flip-flops.

8. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL process example combin : process(state,hg) begin highway_light <= green; end process combin; Sensitivity list Event assignment

9. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL formulas

10. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL data types

11. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Operations in the process if (b or c) = ‘1’ then y <= ‘1’; else y <= ‘0’; if (b or c) = ‘1’ then y <= ‘1’; else z <= a or b; y assigned value in both cases different net assigned in true, false cases

12. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Conditional assignments if (b or c) = ‘1’ then y <= ‘1’; else z <= a or b; Simulation: –Condition is tested based on current signal states. –Only one net gets an event. Synthesis: –Creates don’t-cares for y and z.

13. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Some useful constructs avec: out std_logic_vector(11 downto 0) vector constant zerovec: std_logic_vector(0 to 7) := B”00000000”; constant vector sum <= a + b; adder

14. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Structure of a VHDL model Library use statements. Entity declaration. Architecture declaration. –Processes, etc. that form the architecture. –An entity may have multiple instantiations.

15. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf A synthesizable VHDL archtiecture Declarations of types and signals. Combinational process. –May be several combinational processes that communicate via signals. Synchronous process.

16. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf A synthesizable synchronous process sync: process(CLOCK) begin wait until CLOCK’event and CLOCK = ‘1’; ctrl_state <= ctrl_next; end process sync; Transfers next state to present state Ensures evaluation on clock edge

17. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Testbench structure Unit under test (UUT) testbench tester

18. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf VHDL testbed organization Library calls. Entity declaration. –Generally has no inputs or outputs. Architecture section. –UUT is a component. –Testbench logic is a process.

19. Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Testbench tester process tester: process begin reset <= ‘1’; clock <= ‘0’; wait for 5 ns; clock <= ‘1’; wait for 5 ns; assert(highway_light = green); Clock tick Checks output of UUT