1. ENG6090 RCS1 ENG6090 Reconfigurable Computing Systems Hardware Description Languages Part 1: Introduction

2. ENG6090 RCS2 Topics Review Design Cycle/Flow Review Design Cycle/Flow Hardware Description Languages Hardware Description Languages VHDL History VHDL History Entity/Architecture Entity/Architecture Design Methodologies Design Methodologies

3. ENG6090 RCS3 References –Peter Ashenden, “The designer’s guide to VHDL, 2 nd edition”, Morgan Kaufmann publishers, 2002. –Douglas Perry, “VHDL”, 3 rd Edition, McGraw Hill. –Sudhakar Yalamanchili, “Introductory VHDL: From Simulation to Synthesis”, Prentice Hall, 2001. –Sudhakar Yalamnachili, “VHDL: A Starter’s Guide”, 2 nd Edition, Prentice Hall, 2005.

4. ENG6090 RCS4 Digital System Design Implement Physical Design Logic Design Behavioral Design Structural Design IDEA ASIC Behavioral Simulation Structural Simulation Gate level Simulation Device level Simulation Testing FPGA

5. ENG6090 RCS5 FPGA Design Flow Synthesis Translate Design into Device Specific Primitives Optimization to Meet Required Area & Performance Constraints Design Specification Place & Route Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints Specify Routing Resources to Be Used Design Entry/RTL Coding Behavioral or Structural Behavioral or Structural Description of Design LE MEM I/O RTL Simulation Functional Simulation Verify Logic Model & Data Flow (No Timing Delays)

6. ENG6090 RCS6 Terminology Functional/Behavioral modeling –Describes the functionality of a component/system –For the purpose of simulation and synthesis Structural modeling –A component is described by the interconnection of lower level components/primitives –For the purpose of synthesis and simulation Synthesis: –Translating the HDL code into a circuit, which is then optimized

7. ENG6090 RCS7 Design Abstraction Algorithm RT Language Boolean Eqn or Truth Tab Differential Eqn Transistor Gate RT Proc. Mem. Switch Functional Structural Geometric Polygons Sticks Standard Cells Floorplan Y-Chart

8. ENG6090 RCS8 Schematic Based Flows Grind to a Halt!  Toward the end of the 1980s, as designs grew in size and complexity, schematic-based ASIC flows began to run out of steam.  Visualizing, capturing, debugging, understanding, and maintaining a design at the gate level of abstraction became a tedious task for engineers.  Thus some EDA vendors started to develop design tools and flows based on the use of hardware description languages, or HDLs,

9. ENG6090 RCS9 Traditional Programming Languages  There are wide varieties of computer programming languages (Fortran, C, C++)  Most traditional general-purpose programming languages, such as C, are modeled after a sequential process.  The characteristics of digital hardware, are very different from those of the sequential model:  It is built by smaller parts, with customized wiring  Operations are performed concurrently, and each operation will take a specific amount of time  The sequential model used in traditional programming languages cannot capture the characteristics of digital hardware.  There is a need for special languages (i.e., HDLS) that are designed to model digital hardware.

10. ENG6090 RCS10 What is HDL? model faithfully and accurately  The goal of an HDL is to describe and model digital systems faithfully and accurately.  To achieve this, the cornerstone of the language should be based on the model of hardware operation, and its semantics should be able to capture the fundamental characteristics of the circuits.  Hardware Description Languages (HDLs) are languages used to  document (model),  Communicate design,  simulate, and  synthesize digital circuits and systems.

11. ENG6090 RCS11 Motivation: Documentation Requirements specification - First stage in design is the documentation of system requirements system requirements. - System Requirements: function and performance. - Formal technique via a HDL is desirable.

12. ENG6090 RCS12 Motivation: Communications Design documentation and communication increased design complexity - Due to increased design complexity, a large number of individuals are involved in design. - Formal specification via HDL facilitates easier error free communication of design and error free communication of design. - Formal documentation also aids in maintaining legacy systems.

13. ENG6090 RCS13 Motivation: Simulation Design verification via simulation - The initial requirements specification and actual design can both be simulated with same test stimuli. verifies the - Comparison of the resulting outputs verifies the functionality of the design. functionality of the design.

14. ENG6090 RCS14 Motivation: Synthesis Automated synthesis through computer-aided design tools - Computer aided design tools automatically generate the hardware from the synthesize or generate the hardware from the requirement specification. requirement specification. reduces design time - Automated synthesis reduces design time and eliminates errors due to manual design.

15. ENG6090 RCS15 Motivation for HDL Unifying Philosophy - Maximum reliability in design process at minimum cost and design time.

16. ENG6090 RCS16 VHDL: Introduction VHDL is an acronym for “VHSIC Hardware Description Language”. VHSIC is an acronym for “Very High Speed Integrated Circuits” program. It was a US government sponsored program that was responsible for developing a standard HDL. VHDL supports modeling and simulation of digital systems at various levels of design abstraction.

17. ENG6090 RCS17 VHDL for Specification VHDL for Simulation VHDL for Synthesis of Arithmetic Circuits Synthesizable VHDL

18. ENG6090 RCS18 VHDL: History 1960s – 1980s - number of HDLs mushrooms to over 200 languages. 1983 VHSIC Program initiates definition of VHDL. VHDL Standard 1987 - VHDL Standard (IEEE 1076) approved. 1988 - VHDL begins gain acceptance due to the standardization and DoD efforts.

19. ENG6090 RCS19 VHDL: Introduction 1992 IEEE 1164 (abstract data types for different signal characteristics, eg 9-valued logic) developed. VHDL re-balloted 1993 VHDL re-balloted. - incorporated minor changes for making it user friendly. Since 1994 widespread acceptance of VHDL. - All existing commercial Electronic Design Automation (EDA) tools from Synopsys, Cadence, Mentor etc support specification, simulation and synthesis with VHDL.

20. ENG6090 RCS20 Other HDLs Verilog - very popular - PLI (programming language interface) supports simulation models implemented in C. - Wide support of simulation libraries of ASIC devices. - Lacks higher-level design management constructs like VHDL’s configuration, package and library. SystemC – new Synopsys led initiative - C++ based object oriented framework that supports specification, simulation and synthesis of hardware.

21. ENG6090 RCS21 Digital Circuit Primitives Combinational Logic Gates: NOT, OR, AND Flip Flop/Latch Tri-state Buffer concurrent signal assignments: Logic gates can be modeled using concurrent signal assignments: Z <= not A; Y <= A or B; X <= C and D; W <= E nor F; U <= B nand D; V <= C xor F; It is possible to design circuits from logic gates in this way higher level of abstraction For design entry it is preferable to use other VHDL structures that allow circuit descriptions at a higher level of abstraction X C D AND E F NOR W

22. ENG6090 RCS22 Basic Modeling Concepts B A F Internal Functionality circuit External Interface Inputs Outputs

23. ENG6090 RCS23 Basic Modeling Concepts A B F

24. ENG6090 RCS24 Basic Modeling Concepts External Interface modeled by “entity” VHDL construct. entity AND2 is port (A,B : in bit; F : out bit); end entity AND2; VHDL “port” construct models data input/output. Entity namePort name Port Port mode

25. ENG6090 RCS25 Mode In / Mode Out A Entity Port signal Driver resides outside the entity Port signal Entity Driver resides inside the entity Signal Int can be read inside the entity IntInt C Z Z<= Int C<= Int

26. ENG6090 RCS26 Mode inout Signal can be read inside the entity Entity Port signal Driver may reside both inside and outside the entity A

27. ENG6090 RCS27 Basic Modeling Concepts Internal Functionality modeled by “architecture” VHDL construct architecture dataflow of AND2 is begin F <= A and B; end architecture dataflow; Architecture name Entity name

28. ENG6090 RCS28 Reserved Words  Some identifiers, called reserved words or keywords, are reserved for special use in VHDL.  They are used to denote specific constructs that form a model, so we cannot use them as identifiers for items we define. beginendpackageslauntil entitylibraryportsubtypevariable afterloopprocedurethenwait arraynextsignaltransportwhile

29. ENG6090 RCS29 Lexical Elements Comments: - A comment line in VHDL is represented by two successive dashes “- -”. - A comment extends from “- -” to the end of the line Identifiers: - Identifiers are names that can be given by the user - rules: >> must start with an alphabetic letter. >> can contain alphabetic letters, decimal digits and underline character “_”. >> cannot end with “_”.

30. ENG6090 RCS30 Legal vs. Illegal Identifiers  Valid identifiers A, X0, counter, Next_Value  Invalid identifiers last@value  contains illegal character 5bit_coutner  starts with nonalphabetic _A0  starts with an underline A0_  ends with underline clock__pulses  two successive underlines

31. ENG6090 RCS31 Design Units  Design units are the fundamental building blocks in a VHDL program.  When a program is processed, it is broken into individual design units and each unit is analyzed and stored independently.  There are five kinds of design units Entity declaration Architecture declaration Architecture declaration  Package declaration  Package body  Configuration

32. ENG6090 RCS32 Libraries & Packages Package A Package normally contains a collection of commonly used items, such as data types, subprograms and components, which are needed by many VHDL programs. Each design unit – entity, architecture, configuration package, declaration is analyzed (compiled) and design library placed in a design library. directories Libraries are generally implemented as directories In VHDL we usually use the IEEE library and have to declare that at the beginning of our VHDL program.

33. ENG6090 RCS33 Library: Example For standard logic (std_logic) the basic package is ieee.std_logic_1164. This package defines the values and basic logic operators for type std_logic. The declarations can be made visible in our model file by : library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Library Package

34. ENG6090 RCS34 Complete Program -- Library Declaration library IEEE; use IEEE.std_logic_1164; -- Entity Declaration entity AND2 is Port (A,B : in std_logic; F : out std_logic); end And2; -- Architecture Declaration architecture dataflow of and2 is begin F <= A and B; end architecture dataflow; What is std_logic you ask?

35. ENG6090 RCS35 std_logic type Demystified ValueMeaning ‘U’Not Initialized ‘X’Forcing (Strong driven) Unknown ‘0’Forcing (Strong driven) 0 ‘1’Forcing (Strong driven) 1 ‘Z’High Impedance ‘W’Weak (Weakly driven) Unknown ‘L’ Weak (Weakly driven) 0. Models a pull down. ‘H’ Weak (Weakly driven) 1. Models a pull up. ‘-’Don't Care

36. ENG6090 RCS36 More on std_logic Meanings (1) ‘1’ ‘0’ ‘X’ Contention on the bus Value of all signals at the beginning of simulation Value of all signals that remain un-driven throughout simulation U X

37. ENG6090 RCS37 More on std_logic Meanings (2)

38. ENG6090 RCS38 V DD ‘H’ ‘0’ ‘1’ ‘L’ More on std_logic Meanings (3) V DD

39. ENG6090 RCS39 Examples of Entity Descriptions Q QQ D clk R S op N Z A B C entity ALU32 is port(A, B: in bit_vector (31 downto 0); C : out bit_vector (31 downto 0); Op: in bit_vector (5 downto 0); N, Z: out bit); end entity ALU32; entity D_ff is port(D, Clk, R, S: in bit; Q, Qbar : out bit); end entity D_ff; MSB LSB

40. ENG6090 RCS40 VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral (algorithmic) Registers State machines Test benches Sequential statements Subset most suitable for synthesis

41. ENG6090 RCS41 Entity and Architectures There can be more than one “architecture” or internal functionality descriptions associated with one “entity” declaration. entity and2 is …… architecture dataflow of and2 is …. architecture structural of and2 is …. architecture behavioural of and2 is ….

42. ENG6090 RCS42 Architecture: Introduction architecture behav of and2 is begin …… end architecture behav; dataflow representation In a dataflow representation only concurrent statements exist i.e., f1 <= a and b; f2 <= x or z; behavioral description A behavioral description contains only process (sequential) statements. structural description A structural description contains only component instantiation statements.

43. ENG6090 RCS43 entity and2 is --Three Model Styles port ( a,b in : std_logic; --1. Data Flow f out : std_logic); --2. Structured end and2; --3. Behavioural Many VHDL Descriptions Many VHDL Descriptions architecture dataflow of and2 is begin f <= a and b; end dataflow; architecture structural of and2 is begin u1 : oldand2 port map (a,b,f); end structured; architecture behaviour of and2 is begin and_proc: process (a,b) begin if a = b then f <= ‘1’; else f <= ‘0’; end if; end behaviour;

44. ENG6090 RCS44 Concurrent Statements The concurrent statements are executed without any specific order. The architecture body could contain any combination of concurrent statements. f <= z or w; z <= x and y; x <= not a; w <= a and b; y <= not b;

45. ENG6090 RCS45 Basic Modeling Concepts

46. ENG6090 RCS46 Basic Modeling Concepts External Interface modeled by “entity” VHDL construct. entity ckt1 is port (X,Y,Z : in bit; F : out bit); end entity ckt1; VHDL “port” construct models data input/output. Entity namePort name Port Port mode

47. ENG6090 RCS47 Basic Modeling Concepts Internal Functionality modeled by “architecture” VHDL construct architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav; Architecture name Entity name

48. ENG6090 RCS48 Complete Program -- Library Declaration Library IEEE; Use IEEE.std_logic_1164; -- Entity Declaration Entity ckt1 is Port (X,Y,Z : in std_logic; F : out std_logic); end ckt1; -- Architecture Declaration architecture behav of ckt1 is begin F <= X or not Y and Z; end architecture behav;

49. ENG6090 RCS49 VHDL Design Example Problem: Design a single bit half adder with carry and enable Specifications –Inputs and outputs are each one bit –When enable is high, result gets x plus y –When enable is high, carry gets any carry of x plus y –Outputs are zero when enable input is low x y enable carry Sum Half Adder Y X sum carry

50. ENG6090 RCS50 VHDL Design Example Entity Declaration As a first step, the entity declaration describes the interface of the component –input and output ports are declared x y enable carry sum Half Adder ENTITY half_adder IS PORT( x, y, enable: IN BIT; carry, sum: OUT BIT); END half_adder;

51. ENG6090 RCS51 VHDL Design Example I Behavioral Specification A high level description can be used to describe the function of the adder ARCHITECTURE behavior OF half_adder IS BEGIN PROCESS (x, y, enable) BEGIN IF enable = ‘1’ THEN sum <= x XOR y; carry <= x AND y; ELSE carry <= ‘0’; sum <= ‘0’; END IF; END PROCESS; END behavior;

52. ENG6090 RCS52 VHDL Design Example II Data Flow Specification A second method is to use logic equations to develop a data flow description ARCHITECTURE dataflow OF half_adder IS BEGIN carry <= enable AND (x AND y); sum <= enable AND (x XOR y); END dataflow;

53. ENG6090 RCS53 VHDL Design Example III Structural Specification As a third method, a structural description can be created from predescribed components l These gates can be pulled from a library of parts x y enable carry sum

54. ENG6090 RCS54 VHDL Design Example III Structural Specification (Cont.) ARCHITECTURE structural OF half_adder IS COMPONENT and2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT and3 PORT (in0, in1, in2 : IN BIT; out0 : OUT BIT); END COMPONENT; COMPONENT xor2 PORT (in0, in1 : IN BIT; out0 : OUT BIT); END COMPONENT; FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a); FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a); FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a); -- description is continued on next slide

55. ENG6090 RCS55 VHDL Design Example III S tructural Specification (cont.) -- continuing half_adder_c description SIGNAL xor_res : BIT; -- internal signal -- Note that other signals are already declared in entity BEGIN A0 : and2 PORT MAP (enable, xor_res, sum); A1 : and3 PORT MAP (x, y, enable, carry); X0 : xor2 PORT MAP (x, y, xor_res); END half_adder_c;

56. ENG6090 RCS56 Scope of VHDL in Design Process

57. ENG6090 RCS57