1.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-1 The Grunt Work of Design Many design tasks require a lot of time and effort Forming logic expressions (Truth tables) Reducing logic complexity (Boolean Algebra) Making schematics Analyzing logic circuits Design changes require starting over at the beginning Re-design, Re-do logic reduction, Re-analyze Computers can come to our rescue! Computer Aided Design tools - CAD

2.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-2 CAD Tools In logic design, CAD tools help us in: Design Entry Composing a design in a way that is easily understood by computers and people Logic Synthesis Forming logic equations from higher-level concepts Reducing the complexity of logic equations Simulation Predicting how the resulting circuit will behave Implementation Building an actual circuit for your logic

3.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-3 Design Entry Designs can be entered in many different forms Schematics Truth tables Programming languages Waveforms Combinations of all the above A B CD A B C D a abcF00000011010101111000101111011110abcF00000011010101111000101111011110 f<=(x1 AND x2)OR(NOT(x3 AND x2)); g<=(x1 OR x3)AND(x2 OR (NOT(x1)))

4.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-4 VHDL VHSIC Hardware Description Language Represents digital signals as variables Major parts ENTITY Describes high-level interfaces Inputs and Outputs ARCHITECTURE Describes actual logical function or behavior of circuit

5.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-5 VHDL Entities ENTITY describes high-level interface ENTITY sevensegment IS PORT (A,B,C,D: IN BIT; sa,sb,sc,sd,se,sf,sg: OUT BIT); END sevensegment; Name of ENTITY (note: must be same as file name) Inputs to sevensegment Outputs from sevensegment End of ENTITY WARNING: Syntax is critical and compiler is unforgiving

6.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-6 VHDL Architectures Architecture describes what to actually implement Should describe each output in terms of inputs A B CD A B C D sa ARCHITECTURE LogicFunc OF sevensegment IS sa <= (A OR B OR C OR (NOT D)) AND (A OR (NOT B) OR C OR D); sb <= ….. END LogicFunc; Describing logical function Name of entity this is part of Definition of outputs Function in terms of AND, OR, NOT, NAND, NOR, XOR, XNOR

7.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-7 Synthesis Synthesis – Converting various forms of logic representations into better representations Inputs – Schematics, Truth tables, VHDL, Waveforms Synthesis mechanisms Boolean algebra, related algorithms Outputs – A single logical description of the entire system, in various representation May be optimized according to user-specified criteria Smallest form, Fastest form, etc.

8.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-8 Simulation Simulation predicts how the circuit will perform Functional Simulation Predicts only the logical operation of the circuit Fast Timing Simulation Predicts the actual timing operation of the circuit Requires knowledge of how the circuit will be implemented A B C T1 T2 Z 1 0 1 0 1 0 1 0 1 0 1 0 Inputs 00001111 00110011 01010101 11110000 01110111 01110000

9.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-9 Altera CAD Tools CAD tools that include: Design entry Synthesis Simulation (functional or timing) Implementation (in Altera PLDs and FPGAs) Student version: Implementation portion limited to a small variety of Altera PLDs/FPGAs

10.  Seattle Pacific University EE 1210 - Logic System DesignCAD-VHDL-10 Designing with Altera Quartus 1. Create a new design 2. Input design using various design entry tools Graphical (Schematic) Textual (VHDL, AHDL)Truth Tables Waveforms 3. Synthesize Design (Functional) 4. Functional Simulation 5. Synthesize Design for Implementation 6. Timing Simulation 7. Implement in Hardware Errors? Timing wrong?