1. UW Engineering DOM Studies Kael Hanson University of Wisconsin – Madison LBNL DOM Workshop 23 July 2003

2. 23 July 2003LBNL DOM Workshop2 What Testing was Done? Guiding principle “Attempt to carry out measurements and see how DOM behaves as a data acquisition platform then follow our noses.” Initial measurements desired: –Phototube gain –Peak-to-valley –Phototube noise (not yet /w/ DOM) These measurements implied a priori characterization of DOM analog F.E. Summary of measurements captured in Engineering DOM Tests document.

3. 23 July 2003LBNL DOM Workshop3 DOMs Under Test (DUTs) UW now has 12 DOM-MBs: –5 in ‘active’ DOMs (XE3P0001-0005) –6 in DOMs awaiting testing –1 DOMMB in use by NK for HV base tests 2 DOMMBs returned to LBNL because of hardware problems: –1 flash RAM failure –1 CPLD failure (could not program)

4. 23 July 2003LBNL DOM Workshop4 DUT Configurations Currently all 4 above DOMs running in chest freezer at PSL XE3P0003 is in freezer at Chamberlin undergoing analog tests Full DOM Work-in-Progress table maintained by Jim Hoffman

5. 23 July 2003LBNL DOM Workshop5 ATWD Pedestal Study Purpose –Monitor system electronic noise –ATWD gain calibration Procedure –Set ambient temperature to -20 ºC, … –Set FE bias to various levels –Acquire CPU-triggered ATWD shots

6. 23 July 2003LBNL DOM Workshop6 FE Gain – ATWD Channel 0 Clamping amplifier in ATWD ch0 introduces nonlinearity in analog FE!

7. 23 July 2003LBNL DOM Workshop7 FE Gain – ATWD Channel 1 No clamping amp – linear but ATWD overflows around 1 V – incorrect ATWD tuning parameters here or intentional behavior?

8. 23 July 2003LBNL DOM Workshop8 FE Pedestal/Gain Calibration Proposal If you take delta between 5 th and 1 st curves on previous plot, you would naively expect a flat line. Resulting line is not flat – features persist – do we need separate gain calibration for each ATWD bin? I Is this subscript necessary?

9. 23 July 2003LBNL DOM Workshop9 Pedestal Noise – ISEG DOM 718F PMT HV turned off! max(abs(wfd-ped))

10. 23 July 2003LBNL DOM Workshop10 ATWD Pedestal Noise (2) HV base turned off but ISEG base (718F) just disables HV – power not turned off to base. Disconnecting HV ribbon lowers noise somewhat. Oddly enough, Ch1 shows about same level of noise – would expect 4x less scaling with op- amp gain.

11. 23 July 2003LBNL DOM Workshop11 Pedestal Noise – ISEG DOM 7DAC (ISEG base /w/ no ground wire)

12. 23 July 2003LBNL DOM Workshop12 Pedestal Noise – EMCO DOM 71DB

13. 23 July 2003LBNL DOM Workshop13 Floating Baseline? Tried to test noise with HV on/off but run into problem of wobbling ATWD baseline and odd undershoot at pulse beginning (RHS). (See next page) overall stability of pedestal on 2 hr timescale OK /w/ HV off but HV on causes large rms and drift.

14. 23 July 2003LBNL DOM Workshop14 ATWD Drift vs. Time Approx 2 hr. run time NO HV HV ON

15. 23 July 2003LBNL DOM Workshop15 Summary on Pedestal Testing Significant noise in FE seems due to HV base (no noise seen in DOMMB tests?). Of options EMCO/ISEG, latter produces clearly visible hash in FE while former is clean. Clamping amp nonlinearity significant. Can we tune this away or are we stuck with it? Do we really want to put a clamping amp on any more channels? ATWD channel 1 overflows at about 1 V input (50 pe) – again, is this a tuning problem? Is ATWD FE characterization simply a pedestal fingerprint or do we need more calibration knobs such as individual ATWD bin pedestals and gains.

16. 23 July 2003LBNL DOM Workshop16 Pulser Tests Purpose –Calibrate op-amp gains –SPE/MPE discriminator studies Procedure –Disable HV –Set internal pulser amp to 1/3 pe, 1 pe, … –Do discriminator sweep (FSCAN) –Acquire pulser waveforms

17. 23 July 2003LBNL DOM Workshop17 Pulser Discriminator

18. 23 July 2003LBNL DOM Workshop18 Pulser Waveforms Unable to acquire pulser waveforms with synchronous pulser trigger – advertised in FPGA register level docs but either I called incorrectly or problem at FPGA This type of trigger – synch with FE pulser, LED pulser, LED flasherboard required for some tests.

19. 23 July 2003LBNL DOM Workshop19 SPE Discriminator Scan – PMT Pulses Input (71DB)

20. 23 July 2003LBNL DOM Workshop20 SPE Waveforms CH0 CH1 CH2

21. 23 July 2003LBNL DOM Workshop21 SPE Waveforms (2) Presence of HV again causes drift of front-end baseline. This may be due to ATWD overvoltage –ATWD channel 1 can saturate –ATWD channel 2 seems OK – small drift but probably functional –Why is ATWD channel 0, protected by clamping amplifier, having problems? Current situation with drifting baselines makes analysis of ch0/ch1 waveforms very tricky – hope we can alter the clamping voltage to workaround – need information on this system.

22. 23 July 2003LBNL DOM Workshop22 Gain and P/V Measurement – DOM 0001-3C62-71BD

23. 23 July 2003LBNL DOM Workshop23 Cheap P/V & Gain Analysis Used ATWD ch2 because of baseline wobble – gain of this channel is 2/3× so had to crank HV up to 1600, 1800, 2000 V. Clear P/V appears at 2000 V (apx. 2.2:1) Assuming ATWD gain is 1 mV/count, FE gain is 2/3×, the peak occurs around 40 mV – resulting in gain of about 5 × 10 7 – this just makes target!

24. 23 July 2003LBNL DOM Workshop24 Signal Frequency Analysis

25. 23 July 2003LBNL DOM Workshop25 Conclusions Noise on ISEG HV base is potential trouble – analog tests indicate that level is less than 1 mV p-p but really need to understand characteristics after FE op-amps. Several issues with ATWD-captured waveforms: –‘startup’ bug: 1 st sample after several seconds idle is corrupted – this is more annoying than problematic –Crosstalk from clock when mux’ed into channel 3 – OK once AG explained the problem and the fix. However, crosstalk from ch0 to ch1, ch2 potential problem. Do we test? –Clamping amplifier causes log rolloff of channel 0 –Saturated ATWD inputs cause sizable baseline drift ATWD channel 0 gain seems a bit high – 16x implies approx 100 mV spe, about 100 ATWD counts. Could probably reduce gain by factor of 2, perhaps up to 4.