2. Intro  Scratchpad rings and queues.  First – In – Firs – Out (FIFO) data structure.  Rings are fixed-sized, circular FIFO.  Queues not fixed-size FIFO.

3.  Rings or queues are a common concept in networking for several reasons:  The rates of the tasks producing and consuming on the ring or queue may not be identical.  Multiple producing tasks can be coupled with a single consuming task.  “Multiple processing tasks to all use a single transmit task”  Using multiple rings or queues, a single producing task can be coupled with multiple consuming tasks.  “Some packets require different processing than others”..  Different service preferences can be given to different rings or queues.  “High-priority traffic reserved for us and a second ring may represent all other, best-effort traffic”.

4. Scratchpad Rings  The IXP2XXX hardware supports 16 Scratchpad rings.  Implemented as an array (of configurable size) in scratchpad memory.  With pointers to the first and last entries on the ring, called the head and tail respectively.  The SHaC unit maintains the head and tail pointers, the base address, and the of the ring.  The head and tail pointers are modified during put and get commands on the ring.  Base pointer and size do not change once the ring is created.  Each ring can be configured into one of the four sizes: 128, 256, 512, or, 1024 long-words.

6. Put command.

7. Get command.

8. Creating a Scratchpad Ring  Size of the ring.  Starting scratchpad address where the ring data should reside.  Ring number to use (0-15)

9. Putting Data on a Scratchpad Ring  After creating a scratchpad ring, the code to put data onto a given scratchpad ring is a single instruction, scratch[put, ….].  Ring number  One or more transfer registers  Puts the transfer registers onto the given ring by writing into scratchpad memory.

10. Getting Data from a Scratchpad Ring  The code to get data from a given scratchpad ring is a single instruction, scratch[get, …].  Ring number  One or more transfer registers  Receives the given ring by reading from the scratchpad memory into the transfer registers.

11. Checking for Scratchpad Ring Fullness  Because rings are of fixed size, before putting data on a ring, the fullness of the ring must be checked.  The hardware provides a fullness bit that is not an exact indication of the ring being full.  This bit indicates that the ring has reached the threshold of the three quarters of the total ring capacity.

12.  The fullness bit is set at these thresholds because multiple microengine threads may simultaneously put data on the same ring.  Multiple threads could then check that the ring was not full and issue a putt command.

13. Exact fullness of a ring:  A counter can be maintained in either scratchpad or SRAM memory that corresponds to the number of long-words currently on the ring.  Any thread that performs a put operation would first automatically test and add to this counter.  After a thread performs the scratch[get, …] instruction, if the ring is not empty, the counter is automatically decremented.  The cost : one extra memory operation per put (and get) operation.

14. SRAM Queue Array  Scratchpad rings are not sufficient for applications requiring more than 16 FIFOs.  Scratchpad rings are not sufficient for applications requiring very large FIFOs.  For applications where scratchpad rings are not sufficient, the IXP2XXX processor’s solution is to use SRAM-base FIFOs.  The IXP2XXX hardware can support as many FIFOs as can fit within SRAM memory and provides access to these FIFOs through a 64-element cache (per SRAM controller).  Before a new FIFO can be used, its “descriptor” must be loaded into the “cache” (queue array).

15. Descriptor: contains all of the necessary data to work with the FIFO, such as the head and tail pointers and current number of entries in the FIFO. Each SRAM controller contains a 64-element queue array. Each queue-array element represents a FIFO.

16.  The total number of FIFOs supported is not limited by the size of the SRAM queue arrays, but instead by the amount of SRAM dedicated to the FIFOs.  Each queue-array element contains enough information to add or remove an entry from a single SRAM FIFO. For example, each queue array element contains:  Head pointer.  Tail pointer.  Count of the number of entries currently in the FIFO.

17.  If a new FIFO needs to be loaded and no used queue- array element exists, you must unload an existing queue-array element first.  The unloading process writes the queue-array element into SRAM. To load a queue descriptor, you specify SRAM controller (called a channel), queue- array element number, and SRAM memory from which the descriptor should be loaded.  To unload a queue descriptor, you specify the SRAM controller and queue-array element number. The queue descriptor is written back into the same SRAM location from where it was loaded.

18.  The SRAM controller implements two different types of FIFOs:  linked-list queue.  circular ring.  Scratchpad rings are especially useful following the receive task and into the transmit task.  Don’t need large FIFOs.  Each task requires only one FIFO.  SRAM FIFOs is commonly used within the packet processing stages.