1. Introduction to MOS Transistors Section 6.1-6.4 Selected Figures in Chapter 15

2. Outline Review of NMOS Introduction of PMOS Application of CMOS in Digital Circuits Small Signal Model

3. Introductory Device Physics

4. A Crude Metal Oxide Semiconductor (MOS) Device P-Type Silicon is slightly conductive. Positive charge attract negative charges to the interface between insulator and silicon. A conductive path is created If the density of electrons is sufficiently high. Q=CV. V2 causes movement of negative charges, thus current. V1 can control the resistivity of the channel. The gate draws no current!

5. Typical Dimensions of MOSFETs These diode must be reversed biased. tox is made really thin to increase C, therefore, create a strong control of Q by V.

6. A Closer Look at the Channel Formulation Need to tie substrate to GND to avoid current through PN diode. Positive charges repel the holes creating a depletion region, a region free of holes. Free electrons appear at V G =V TH. V TH =300mV to 500 mV (OFF)(ON)

7. VG-VD is sufficiently large to produce a channel VG-VD is NOT sufficiently large to produce a channel No channel Electrons are swept by E to drain. Drain can no longer affect the drain current!

8. Regions No channel (No Dependence on VDS) Assumption:

9. Graphical Illustration

10. Determination of Region TYPO: ON

11. Determine Region of Operation (6.19) Tricky! Assume that V THN =0.4 V and V THP =-0.4 V

12. PMOS in Cut-Off Mode P+P+ P+P+ N P N+N+ Substrate= 0V - - - - -

13. PMOS: Formation of Channel P+P+ P+P+ N P N+N+ Substrate= 0V Induced holes ++++++++++ - - - - -

14. PMOS in Triode Region P+P+ P+P+ N P N+N+ Substrate= 0V Induced holes - - - - +++++++++

15. PMOS in Saturation Region P+P+ P+P+ N P N+N+ Substrate= 0V Induced holes - - - - - - - ++++++++

16. PMOS Transistor

17. Determine Region of Operation (6.40) Assume that V THN =0.4 V and V THP =-0.4 V

18. NMOS Inverter VGS=VCC, Switch is ON. VGS=0 V, Switch is OFF.

19. PMOS Inverter VSG=VCC, switch is off. VSG=0, switch is on.

20. Mysterious 2-Input Logic Gate

21. Exercise In Class

22. NAND Gate

23. Small Signal Model

24. Limited VDS Dependence In Saturation As VDS increase, effective L decreases, therefore, ID increases.

25. Pronounced Channel Length Modulation in small L

26. Similarity to Early Effect A larger reverse bias voltage leads to a larger BC depletion region. The effective base width (WB) is reduced. The slope of the electron profile increases. I C increases as VCE is increased.

27. Output Resistance

28. Transconductance As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance: It is important to know that

29. Compare NMOS Equation to PMOS Equation Valid for NMOS Valid for PMOS (Cut-off) (triode) (saturation) (triode) (Cut-off) (saturation)

30. Small Signal Model for Both BJT AND CMOS

31. Exercise Slides

32. Determine Region of Operation (6.19) Tricky! Assume that V THN =0.4 V and V THP =-0.4 V

33. Determine Region of Operation (6.40) Assume that V THN =0.4 V and V THP =-0.4 V

34. NMOS Inverter VGS=VCC, Switch is ON. VGS=0 V, Switch is OFF.

35. PMOS Inverter VSG=VCC, switch is off. VSG=0, switch is on.

36. Mysterious 2-Input Logic Gate

37. Exercise In Class

38. Optional Slides

39. VA=5 V

40. VA=0 V