1. Providing Infrastructure for Optical Communication Networks
EECS 294 Colloquium
4 October 2006
Prof. Michael Green
Dept. of EECS
Henry Samueli School of Engineering
This presentation can be found at:

2. Friday, March

3. Advantages of Optical Fibers over Copper Cable
Very high bandwidth (bandwidth of optical transmission network determined
primarily by electronics)
Low loss
Interference Immunity (no antenna-like behavior)
Lower maintenance costs (no corrosion, squirrels don’t like the taste)
Small & light: feet of copper weighs approx. 300 lb.
1000 feet of fiber weighs approx. 10 lb.
Different light wavelengths can be multiplexed onto a single fiber:
Dense Wavelength Division Multiplexing (DWM)
10Gb/s transmission networks now being deployed;
40Gb/s will be here soon.

4. Protocols for High-Speed Optical Networks
Synchronous Optical Network (SONET):
Provides a protocol for long-haul (50-100km) wide-area netework
(WAN) fiber transmission
Basic OC-1 rate is 51.84Mb/s
OC-48 (2.5Gb/s) & OC-192 (10Gb/s) are common
Gigabit/10 Gigabit Ethernet (IEEE Standard 802.3):
Ethernet was invented in 1973 at Xerox PARC
(“ether” is the name of the medium through which E/M waves were thought to travel)
Provides a protocol for local-area network (LAN) copper or fiber
transmission
1 Gb/s links can be transmitted over twisted-pair copper
10 Gb/s links can be transmitter over copper (short lengths) or
fiber.

5. Fiber Channel:
Often used for Storage Area Networks (SAN); allows fast
transmission of large amounts of data across many different
servers.
Currently 1-4 Gb/s is deployed; 8Gb/s will arrive soon.

6. Some SAN Terminology JBOD: Just a Bunch Of Disks
Refers to a set of hard disks that are not configured
together.
RAID: Redundant Array of Independent (or Inexpensive?) Disks
Multiple disk drives that are combined for fault tolerance
and performance. Looks like a single disk to the rest of
the system. If one disk fails, the systems will continue
working properly.

7. Blade Servers vs. Regular Servers
Blades take up less room, consume less power, and are hot-swappable. They are configured like books on a shelf.
Carries only the essentials: motherboard w/processor, memory, networking circuitry, hard drive
No cables; connections are by built-in connectors.
Highly modular and configurable.
See:
for full article.

8. Barcelona, Spain: MareNostrum supercomputer cluster (2282 Blade servers)
Mare Nostrum -- “our sea” signifies the location and vastness of the computing resource.
Housed in Chapel Torre Girona (Technical Univ. of Catalonia)

9. Characteristics of Broadband Signals & Circuits
Primarily digital (i.e., bilevel) operation but high bit rate (multi-Gb/s)
dictates analog behavior & design techniques.
Standard analog circuit applications:
Continuous-time operation
Precision required in signal domain (i.e., voltage or current)
Dynamic range determined by noise & distortion
Broadband communication circuits:
Discrete-time (clocked) operation
Precision required in time domain
(low jitter)
Bilevel signals processed t V t0 V
Gives general characteristics of standard digital, standard analog, and broadband signals. t V t Vh Vt Vl

10. Typical broadband data waveform:
Length of single bit = 1 Unit Interval (1 UI)
Eye diagram
An eye diagram maps a random bit sequence to a regular structure that can be used to analyze jitter.

11. Close-up of eye diagram:
trise = tfall
voltage swing
1 UI
Zero crossings

12. What is Jitter?
Jitter is the short-term variation of the significant instants of a digital signal from their ideal positions in time.
Jitter normally characterizes variations above 10Hz; variations below 10Hz are called wander.
The effects of these variations are measured in 3 ways:
Phase noise (frequency domain)
Jitter (time domain)
Bit Error-Rate (end result of phase noise & jitter)

13. Types of Jitter Random Jitter (RJ)
Originates from external and internal random noise sources
Stochastic in nature (probability-based)
Measured in rms units
Observed as Gaussian histogram around zero-crossing
Grows without bound over time
Histogram measurement at zero crossing
exhibiting Gaussian probability distribution

14. Types of Jitter (cont.) Deterministic Jitter (DJ)
Originates from circuit non-idealities (e.g., finite bandwidth, offset, etc.)
Amount of DJ at any given transition is predictable
Measured in peak-to-peak units
Bounded and observed in various eye diagram “signatures”
Different types of DJ:
Intersymbol interference (ISI)
Duty-cycle distortion (DCD)
Periodic jitter (PJ)

15. a) Intersymbol interference (ISI)
Consider a 1UI output pulse from a buffer:
1UI
< 1UI
If rise/fall time << 1 UI, then the output pulse is attenuated
and the pulse width decreases.

16. ISI (cont.) Consider 2 different bit sequences: 1 1 11 1 1
Steady-state not reached
at end of 2nd bit
t = ISI
2 output sequences
superimposed
ISI is characterized by a double edge
in the eye diagram. It is measured in units of ps peak-to-peak.

17. Effect of ISI on eye diagram:
Double-edge

18. b) Duty cycle distortion (DCD)
Occurs when rising and falling edges exhibit different delays
Caused by circuit mismatches
Nominal data sequence
Data sequence with early falling edges
& late rising edges
t = DCD
Eye diagram with DCD
Crossing offset from
nominal threshold

19. c) Periodic Jitter (PJ)
Timing variation caused by periodic sources unrelated to the data pattern.
Can be correlated or uncorrelated with data rate.
t1
t0
Clock source with
duty cycle
Synchronized data
exhibiting correlated PJ
Uncorrelated jitter (e.g., sub-rate PJ due to supply ripple) affects the eye diagram in a similar way as RJ.

20. Jitter and Bit Error RateT R
Probability of sample at t > t0 from left-hand transition:
Probability of sample at t < t0 from right-hand transition:

21. Total Bit Error Rate (BER) given by:

22. Example: T = 100ps log(0.5) log BER t0 (ps) (64ps eye opening)

23. Bathtub Curves
The bit error-rate vs. sampling time can be measured directly using a bit error-rate tester (BERT) at various sampling points.
Note: The inherent jitter of the analyzer trigger should be considered.

24. Benefits of Using Bathtub Curve Measurements
Curves can easily be numerically extrapolated to very low BERs (corresponding to random jitter), allowing much lower measurement times.
Example:
10-12 BER with T = 100ps is equivalent to an average of 1 error per 100s. To verify this over a sample of 100 errors would require almost 3 hours!
t0 (ps)

25. Deterministic jitter and random jitter can be distinguished and measured by observing the bathtub curve.

26. CMOS Fabrication Process
Advantages of Using
CMOS Fabrication Process
Compact (shared diffusion regions)
Very low static power dissipation
High noise margins (nearly ideal inverter voltage transfer
characteristic)
Very well modeled and characterized
Inexpensive (?)
Mechanically robust
Lends itself very well to high integration levels
SiGe BiCMOS has many advantages but is a generation behind
currently available standard CMOS

27. CMOS gates generate and are sensitive to supply/ground bounce.
Series R & L cause supply/ground bounce.
Resulting modulation of transistor Vt’s results in jitter.

28. Rs = 5W Ls = 5nH Rs = 0 Ls = 0 Rs = 5W Ls = 5nH clock out clock out
data in
data out
clock in
clock out
Rs = 5W Ls = 5nH
clock out
Rs = 0
Ls = 0
clock out
Rs = 5W
Ls = 5nH
data out

29. Inverter based on differential pair:
Differential operation
Inherent common-mode rejection
Very robust in the presence of common-mode
disturbances (e.g., VDD/VSS bounce)
“Current-mode logic (CML)”

30. Rs = 5W Ls = 5nH Rs = 0 Ls = 0 Rs = 5W Ls = 5nH clock out clock out
data in
data out
clock in
clock out
Rs = 5W Ls = 5nH
clock out
Rs = 0
Ls = 0
clock out
Rs = 5W
Ls = 5nH
data out

31. Research Topics BiCMOS 10Gb/s Adaptive Equalizer
A Novel CDR with Adjustable Phase Detector Characteristics
A Distributed Approach to Broadband Circuit Design

32. Research Topics
BiCMOS 10Gb/s Adaptive Equalizer
Evelina Zhang, Graduate Student Researcher
A Novel CDR with Adjustable Phase Detector Characteristics
A Distributed Approach to Broadband Circuit Design

33. Cable Model Where: L is the cable length
magnitude (dB)
+10
shorter cable
Copper Cable
-10
longer cable
-20
-30
100M 1G
10G f
phase (deg)
In high speed digital communications, Data signal coming after a copper cable will get distorted. Typically they are suffered from skin effect loss and dielectric loss. In frequency as high as 5GHz, skin effect loss dominates.for example, a cable length of as little as 3 foot has bandwidth significantly lower than the data baud rate of 5Ghz. The cable transfer function can be modeled as the exponential function of the cable length ,cable charateristic and the square root of the frequency. The magnitude of two different length of cable is plotted v.s. frequency. It is not hard to see longer cable has more loss near 5Ghz.
The equalizer is designed as a filter whose transfer function should be set over an appropriate frequncy range, equal to the inverse of the connecting cable transfer function..
Possible questions:
Why do we look at the 5ghz point?
(where do you get this model ? Why is it like that ? How did you model your circuit? What length is that? )
shorter cable
-100
Where: L is the cable length
a is a cable-dependent characteristic
longer cable
-200
-300
100M 1G
10G f

34. Motivation Improve receiver sensitivity Reduce ISI input waveform (V)
0.5
input eye
0.5
-0.5
-0.5
300 39 40 41 42 43
100
200
t (ns)
t (ps)
output waveform (V)
output eye
0.3
0.3
Here comes the motivatio of our research on equalizer. the job of equalizer is to combat Intersymbol interference and therefore improve the sensitivity of of the receiver. this is a simulated outout waveform after the cable for a 10Gb/s data. It is not hard to see the signal after the cable has severe ISI due to the high frequency loss. . Take a look at that small pulse , whose amplitude even almost didn’t reach half voltage swing. If we apply signal like this quality directly to the receiver , it will of course make wrong decision and therefore bit errors occur . A common tool for visulizing the nonidealities in random data is eyediagram. We can see the eye is totally closed. It would be nice if we design a system that resetore the waveform and…open the eye.
Possible questions:
what is an eye diagram? How did u generate it? Why is it usefull here?
How did you model your cable to generate the eye diagram?
-0.3
-0.3
100
200
300 39 40 41 42 43
t (ps)
t (ns)

35. Adaptive Equalizer Implemented in Jazz Semiconductor SiGe process:
120GHz fT npn
0.35m CMOS

36. Equalizer Block Diagram

37. Feedforward Path

38. FFE Frequency Response
Vcontrol
This figure shows the simulated ac response for 3 different values of Vcontrol.
The upper curve coresponds to a lower Vcontrol. We have noted that the equalization setting primarily affects the low frequency gain
f (Hz)

39. ISI & Transition Time VFFE t (ns)
0.3
teq = 45ps
PW = 108ps
teq = 60ps
PW = 100ps
teq = 75ps
PW = 86ps
-0.3
2.4
2.5
2.6
2.7
2.8
t (ns)
Simulations indicate that ISI correlates
strongly with FFE transition time teq.
Optimum teq is observed to be 60ps.

40. Slicer
This slicer is implemented by two cascaded CML buffers. The first buffer ehibits fast transition time and corrects the signal amplitude. This limiting is critical because the equalizer output exhibits large over shoots even when the ISI is minimized. The second buffer produces an output with a fixed transition time that optimize the output ISI. This optimal transition time is achieved when the obseved output exhibits the lowest ISI.
Possible questions:
how did you find the optimal rise fall time? How can you tell for difference cable?

41. Feedback Path
The feedback path is shown here where you can see the two detectors are designed to give an output pulse whose engergy is proportional to the input transition time. The pulses are then applied to the differential inputs of an integrator. The integrator output resonds to the difference of the transition time between the detector inputs. When the adaptive loop reaches steady state, v control will be set such that the equalizer output will exhibit the same transition time as the slicer output.

42. Transition Time Detector
DC characteristic:
Transient Characteristic:
(b)
(a)
(b)
(a) t
Rectification & filtering done in a single stage.

43. Integrator
The integraor , designed using standard CMOS techniques, gives an output control voltage Vcontrol that is proportional to the energy in the pulsesat the output of the detectors. This voltage is the fed back to the equalizer. A common mode feedback is designed to improve the stability. The transfer function of the integrator can be approximated as:
where……….

44. Detector + Integrator FFE transition Time tFFE Vcontrol (mV) 90ps 75ps
From
FFE
tFFE
From
Slicer
tslicer=60ps
Vcontrol (mV)
90ps 60
slope
detector
slope
detector 40
75ps 20
60ps
-20
45ps
-40
-60
15ps 10 20 30 40 50 _ +
t (ns)
Vcontrol

45. System Analysis Kd H(s) Keq Kd Keq = 1.5 ps/mV Kd = 2.5 mV/ps
integrator
tslicer
feedforward
equalizer
detector
Vcontrol
teq + Kd
H(s)
Keq _
detector Kd
Keq = 1.5 ps/mV
Kd = 2.5 mV/ps
tint = 75ns

46. Measurement Setup Die under test 231 PRBS signal applied to cable
EQ inputs
Die under test
EQ outputs
231 PRBS signal
applied to cable

47. Eye Diagrams EQ output EQ input 4.0ps rms jitter 3.9ps rms jitter
4-foot
RU256 cable
4.0ps rms jitter
15-foot
RU256 cable
3.9ps rms jitter

48. Summary of Measured Performance
Supply voltage
3.3V
Power Dissipation
350mW
(155mW not including output driver)
Die Size
0.81mm X 0.87mm
Output Swing
490mV single-ended p-p
Random Jitter
4.0ps rms (4-foot cable)
3.9ps rms (15-foot cable)
This table is the summary of measured performance. (read the table)

49. Ongoing Research Investigate transition detector more thoroughly
Understand trade-off between ISI reduction and random jitter generation
Investigate compensation of PMD in optical fiber

50. Random noise in Analog Equalizer
output eye
ISI: 6.2ps p-p
input eye
(no noise added)

51. ISI+random jitter: 23ps p-p input eye with added noise
output eye
ISI+random jitter: 23ps p-p
input eye with added noise
ISI is reduced but random jitter is increased due to
amplification of random noise.

52. Decision Feedback Equalization (DFE)

53. Summing circuit:
Variable delay circuit:

54. DFE Simulations (copper)
output eye
no noise added
ISI: 6.7ps p-p
output eye
random noise added
ISI+random jitter: 7.4ps p-p

55. DFE Simulations (fiber)
input waveform
exhibiting PMD
input eye
output eye
ISI: 7.9ps p-p

56. Research Topics BiCMOS 10Gb/s Adaptive Equalizer
A Novel CDR with Adjustable Phase Detector Characteristics
Xinyu Chen, Graduate Student Researcher
A Distributed Approach to Broadband Circuit Design

57. Clock/Data Recovery Circuits
Ability to handle high bit rates
Low jitter generation
High jitter tolerance
Fast acquisition
CDR Requirements:
Binary
operation
Linear
operation

58. 2-Loop CDR Architecture
Is it possible for a CDR to exhibit linear (quiet) behavior and fast acquisition with a single loop?

59. “Ternary” latch:
Deadband PD
characteristic

60. CML version:
external
control

61. Comparisons

62. Conventional Binary PD
Simulation Results
Conventional Binary PD
Hogge PD
Ternary PD;
VG = 1.65V
Ternary PD;
VG = 1.75V

63. Varying VG During Acquisition

64. Future Work
Using the variable PD characteristic as part of a lock detection circuit.
Minimizing jitter in a similar way.

65. Research Topics BiCMOS 10Gb/s Adaptive Equalizer
A Novel CDR with Adjustable Phase Detector Characteristics
A Distributed Approach to Broadband Circuit Design
Ullas Singh, Graduate Student Researcher

66. Distributed Amplifier
Signals travel ballistically through amplifier.
Higher gain-bandwidth product.
Naturally drives resistive load.
Trades off delay for bandwidth.

67. Distributed Frequency Divider
Buffer delay of lumped elements can be replaced by passive element delay in distributed divider
All simulations
used 0.18m CMOS
Lumped frequency divider schematic
Distributed divider schematic

68. Distributed Frequency Divider Simulations
Divider sensitivity
curve
Input/Output waveform

69. Frequency Divider Layout
Area=800mm*807mm

70. Distributed 2-to-1 Select Circuit
Lumped select circuit
Timing diagram
Proposed distributed select circuit

71. distributed circuitry
40Gb/s MUX Block Diagram
10Gb/s
20Gb/s
40Gb/s
PRBS
generator
4:2
MUX
2:1
MUX
lumped circuitry
distributed circuitry
(180nm CMOS)

72. Simulated 40Gb/s Eye Diagram
Vout (V)
0.6
0.4
0.2
-0.2
-0.4
-0.6 10 20 30 40 50 60 70 80
t (ps)
ISI: 2ps (80mUI) p-p

73. Test Setup
die bonded
directly to
board

74. Measured Results Bit-rate: 34Gb/s (due to varactor variations)
Measurements taken with Agilent C DCA-J with 80GHz plug-in module

75. Future Research
Analyze nonlinear large-signal effects & derive a clear design methodology.
Investigate possible methods of electrically (or optically?) controlling characteristic impedances of tranmission lines.