1. Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic

2. Today Dynamic Logic –Strategy –Form –Compare CMOS w/ and w/out diffusion capacitance Penn ESE370 Fall2010 -- DeHon 2

3. Motivation Still like to avoid driving pullup/pulldown networks –reduce capacitive load Power, delay

4. Motivation Still like to avoid driving pullup/pulldown networks –reduce capacitive load Power, delay Ratioed had problems with –Large device for ratioing –Slow pullup –Static power

5. Idea Use clock to disable pullup during evaluation

6. Advantages Large device –Driven by clock not data/logic –Can pullup quickly w/out putting load on logic Single network –pulldown

7. Domino Logic

8. Domino Everything charged high –After inverter all inputs low Disabled, waiting for an enabling transition Penn ESE370 Fall2010 -- DeHon 8

9. Requirements Single transition –Once fires, it is done  like domino falling All inputs at 0 during precharge –Precharge to 1 so inversion makes 0 Non-inverting gates http://en.wikipedia.org/wiki/File:Domino_effect.jpg

10. Issues Noise sensitive Power? Activity?

11. Domino or4

12. Domino Logic Perfromance –R 0 /2 input Compare to CMOS cases? nor4 or4 nand4 Look at C diff =0 and C diff =C gate

13. C diff =0 cases  N =2.5  P Penn ESE370 Fall2010 -- DeHon 13

14. Dynamic OR4 Precharge time? Driving input –With R 0 /2 Driving inverter? Penn ESE370 Fall2010 -- DeHon 14

15. CMOS NOR4 Driving input –With R 0 /2 Driving (5,2) inverter Penn ESE370 Fall2010 -- DeHon 15

16. CMOS NAND4 Driving input –w/ R 0 /2 Penn ESE370 Fall2010 -- DeHon 16

17. C diff =C gate cases  N =2.5  P Penn ESE370 Fall2010 -- DeHon 17

18. Dynamic OR4 Precharge time? Driving input –With R 0 /2 Driving inverter and self cap? Output self delay? Penn ESE370 Fall2010 -- DeHon 18

19. CMOS NOR4 Driving input –With R 0 /2 Driving self cap? Driving (5,2) inverter Penn ESE370 Fall2010 -- DeHon 19

20. CMOS NAND4 Driving input –w/ R 0 /2 Driving self cap? Penn ESE370 Fall2010 -- DeHon 20

21. Discuss (time permit) Avoid inversion? Converting from CMOS? Post-charge Penn ESE370 Fall2010 -- DeHon 21

22. Observe Better (lower) ratio of input capacitance to drive strength Particularly good for –Driving large loads –Large fanin gates Harder to design with –Timing and polarity restrictions –Avoiding noisy Can consume more energy/op Penn ESE370 Fall2010 -- DeHon 22

23. Admin Normal lectures this week Midterm –Graded – Mean 69 –Solutions posted Andre out Tuesday –No office hours Penn ESE370 Fall2010 -- DeHon 23

24. Idea Dynamic/clocked logic –Only build/drive one network –Fast transition propagation –Spend delay (capacitance) on pullup off critical path of logic –More complicated, power Reserve for when most needed Penn ESE370 Fall2010 -- DeHon 24