1. Notes on Transistor Sizing for equal pullup/pulldown We assume that electron mobility to hole mobility ratio is 2 in this class. This means that a minimum sized PMOS has an effective resistance twice that of a minimum sized NMOS. Resistance inversely proportional to width Make PMOS transistor width twice that of NMOS to get same channel resistance

2. Sizing: 4-input NOR

3. Sizing: 3-input NAND

4. Sizing Example: Complex Gate Each individual path to Vdd/GND is considered separately. Want the effective resistances of the transistors along the path to sum to R; need to determine width (k) for each transistor.

5. Sizing Example: Complex Gate, Solution 1

6. Sizing Example: Complex Gate, Solution 2 Previous solution is slightly better as it has less total gate width and loading on three of four inputs is smaller.