1. Fetch-execute cycle

2. Fetch decode & execute cycle
There are three main parts to this process:
Fetch
Retrieves the instruction that is required to be used
Decode
The instructions is interpreted and broken down into it’s constituent parts (eg opcode / operand)
Execute
The instruction is performed and carried out.
Fetch-execute cycle

3. Fetch decode & execute cycle
Instructions called into the processor from main memory having been fetched and decoded.
Instruction
Instruction
Instructions being fetched, decoded and executed.
Data
Processor
Data
Instruction
Main memory
Processor
Fetch-execute cycle

4. Fetch cycle Program Counter +1
Points to the next instruction that needs to be executed. It is incremented by one to point to the next instruction
Program Counter PC
Fetch cycle

5. Memory Address Register (MAR) Memory Address Register (MAR)+1
The memory address register (MAR) holds the address of the currently addressed memory location.
Program Counter PC
Memory Address Register (MAR)
Fetch cycle

6. Memory Address Register (MAR)+1
Program Counter PC
Address
Bus
Memory Address Register (MAR) 1
Data 2
Data 3
ADD #6
Main Memory 4
Data
The Memory Address Register (MAR) points the next instruction in main memory. 5
Data 6
Data
Main memory
Fetch cycle

7. Fetch cycle Memory Data Register (MDR) +1
Program Counter PC
Address
Bus
Memory Address Register (MAR) 1
Data 2
Data
Data
Bus
Memory Data Register (MDR) 3
ADD #6 4
Data
Memory Data Register (MDR) 5
Data
The instruction is located and loaded into the memory data register (MDR) also called the MBR. 6
Data
Main memory
Fetch cycle

8. Fetch cycle Current Instruction Register (CIR) +1
Program Counter PC
Address
Bus
Memory Address Register (MAR) 1
Data
Data
Bus 2
Data
Memory Data Register (MDR) 3
ADD #6 4
Data
Current Instruction Register (CIR) 5
Data 6
Data
Current Instruction Register (CIR)
The instruction resides in the Current Instruction register (CIR). This is the end of the ‘fetch’ part of the cycle.
Main memory
Fetch cycle

9. +1
Decode
Program Counter PC
The instruction in the current instruction register (CIR) is decoded.
Address
Bus
Memory Address Register (MAR) 1
Data
Data
Bus 2
Data
Memory Data Register (MDR) 3
ADD #6 4
Data
Current Instruction Register (CIR) 5
Data 6
Data
Decodes the instruction
Main memory
Instruction decoder
Decode cycle

10. +1
Decode
The instruction is separated into the opcode and the operand as part of this process.
Program Counter PC
Address
Bus
Memory Address Register (MAR) 1
Data
Data
Bus 2
Data
Memory Data Register (MDR) 3
ADD #6 4
Data
Current Instruction Register (CIR) 5
Data 6
Data
Instruction decoder
Op-code
Operand
Main memory
Decode cycle

11. Execute cycle Execute ALU +1
The fetched and decoded instruction is now executed to complete the process.
Program Counter PC
Address
Bus
Memory Address Register (MAR) 1
Data
Data
Bus 2
Data
Memory Data Register (MDR) 3
ADD #6 4
Data
Current Instruction Register (CIR) 5
Data 6
Data
Instruction decoder
Op-code
Operand
Main memory
ALU
Accumulator
Finally executes the instruction
Execute cycle