2. Copyright © 1997 Altera Corporation 11/26/2015 P.1 Usage of FloorPlanner Danny Mok Altera HK FAE (dmok@altera.com)

3. Copyright © 1997 Altera Corporation 11/26/2015 P.2 What is the Floorplan It is use to control the placement of your design logic –to increase the performance of your design –to reduce the ROW/COLUMN traffic –resolve the “can not fit” issue (Altera Expert can do this for you) –use to control the trace delay Logic Plan can not help you to simplify your design from a Complex to a Simple one

4. Copyright © 1997 Altera Corporation 11/26/2015 P.3 Why the Floorplan is so important The Delay is a combinational of Two Factors –Gate Delay –Trace Delay Two situation to consider –Gate Delay >>>> Trace Delay (floorplan is useless, logic complexity is more important) –Gate Delay <<<< Trace Delay (floorplan is very important) For Altera Device, Trace Delay is bigger than Gate Delay, so floorplan is important Trace Delay Gate Delay

5. Copyright © 1997 Altera Corporation 11/26/2015 P.4 Example 1

6. Copyright © 1997 Altera Corporation 11/26/2015 P.5 Example 2 11.7 - 2.4 = 9.3ns delay caused by TRACE DELAY

7. Copyright © 1997 Altera Corporation 11/26/2015 P.6 What Altera Floorplan can do Altera Floorplan can provide the designer to control –the I/O pin location –the logic cell location For the I/O pin, you can control the location at –different Row –different Column For the Logic Cell, you can control the location at –different cell within LAB –different LAB –different Row –different Column

8. Copyright © 1997 Altera Corporation 11/26/2015 P.7 cont... Before use the Floorplan to control the placment, you must back-annotate the project first –you have the choice to lock down the Pin and Logic Cell lock down the Logic Cell

9. Copyright © 1997 Altera Corporation 11/26/2015 P.8 Back-Annotate the Project is the First Step Click on this button

10. Copyright © 1997 Altera Corporation 11/26/2015 P.9 I/O Location Control - Method 1 Change the Last Compilation to Current Compilation

11. Copyright © 1997 Altera Corporation 11/26/2015 P.10 Drag and Place Anywhere of the Device Any where within this row Anywhere within this column At this particular I/O pin

12. Copyright © 1997 Altera Corporation 11/26/2015 P.11 Method 2 Drag and Drop the I/O pin signal to any location which you want

13. Copyright © 1997 Altera Corporation 11/26/2015 P.12 Logic Cell assignment Anywhere of the Device Any where within this row Anywhere within this LAB At this particular LC Anywhere within this column

14. Copyright © 1997 Altera Corporation 11/26/2015 P.13 Summary All the I/O pin and Logic Cell must work at “Current Assignment” window Use the Drag & Drop method to make the assignment Playing around with Floorplan is not easy, more than 90% of the design does not need to touch the floorplan