1. FLCC 11/06/2006 Device 1 Spacer Lithography for Reduced Variability in MOSFET Performance Prof. Tsu-Jae King Liu Electrical Engineering & Computer Sciences Dept. University of California at Berkeley Graduate Student: Ms. Xin Sun FLCC Seminar

2. FLCC 11/06/2006 Device 2 Outline Introduction –MOSFET scaling –Lithography challenges Spacer Lithography Device Simulation Study Summary and Future Work

3. FLCC 11/06/2006 Device 3 Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistor IC Technology Advancement Better Performance/Cost Market Growth International Technology Roadmap for Semiconductors Transistor Scaling Investment SMIC’s Fab 4 (Beijing, China) Photo by L.R. Huang, DigiTimes YEAR:20042007201020132016 HALF-PITCH:90nm65nm45nm32nm22nm PITCH

4. FLCC 11/06/2006 Device 4 The Bulk-Si MOSFET Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode Substrate Gate SourceDrain Metal-Oxide-Semiconductor Field-Effect Transistor: GATE LENGTH, L g OXIDE THICKNESS, T ox JUNCTION DEPTH, X j M. Bohr, Intel Developer Forum, September 2004 Desired characteristics: High ON current Low OFF current “N-channel” & “P-channel” MOSFETs operate in a complementary manner “CMOS” = Complementary MOS |GATE VOLTAGE| CURRENT VTVT

5. FLCC 11/06/2006 Device 5 V T Roll-Off |V T | decreases with L g –Effect is exacerbated by high values of |V DS | Qualitative explanation: –The source & drain p-n junctions assist in depleting the Si underneath the gate. The smaller the L g, the greater the percentage of charge balanced by the S/D p-n junctions: M. Okuno et al., 2005 IEDM p. 52 Large L g : S D Small L g : DS

6. FLCC 11/06/2006 Device 6 Sub-Threshold Leakage Leakage current varies exponentially with V T S ≥ 60mV/dec at room temperature, due to thermal distribution of carriers within energy bands –typically 80-100 mV/dec for a bulk-Si MOSFET log I D VGVG I OFF, high VT V DD I OFF, low VT I ON, low VT I ON, high VT S 0

7. FLCC 11/06/2006 Device 7 Parametric Yield High-performance processors are speed-binned –Faster chips = more $$$ (These parts have smaller L g ) Leakage is exponentially dependent on V T = f(L g ) Since leakage is now appreciable, parametric yield is being “squeezed” on both sides TOO SLOW TOO LEAKY smaller L gate  Tighter control of L g will be needed with scaling!

8. FLCC 11/06/2006 Device 8 The Sub-Wavelength Gap

9. FLCC 11/06/2006 Device 9 Achieving Sub-Wavelength Resolution courtesy M. Rieger (Synopsys, Inc.)

10. FLCC 11/06/2006 Device 10 Geometrical Regularity for Improved Yield A geometrically regular layout should be used to improve the fidelity of printed sub-wavelength features. –All MOSFETs are oriented along the same direction –Gate lines are placed at regular spacings L. Pillegi et al., 2003 DAC p. 782 Configurable logic block layout

11. FLCC 11/06/2006 Device 11 Mask Cost Considerations Mask cost escalates with technology advancement!  It will eventually be more cost effective to use multiple lower-cost masks to define the most critical layer (gate) < (minimum half-pitch)

12. FLCC 11/06/2006 Device 12 Outline Introduction Spacer Lithography –Process flow –Application to gate patterning Device Simulation Study Summary and Future Work

13. FLCC 11/06/2006 Device 13 Spacer Lithography Process gate dielectric poly-Si gate layer a-Si 1. Deposit & pattern sacrificial layer Note that pitch is 2  that of patterned layer! hard mask (SiO 2 ) L g,min gates Si gate dielectric poly-Si gate layer 2. Deposit mask layer (e.g. Si 3 N 4 ) a-Si hard mask (SiO 2 ) Si gate dielectric poly-Si gate layer 3. Anisotropically etch mask layer a-Si hard mask (SiO 2 ) spacers Si 4. Remove sacrificial material; Etch hardmask and poly-Si gate dielectric Si

14. FLCC 11/06/2006 Device 14 2 n lines after n iterations of spacer lithography! 1st Spacers2nd Spacers 3rd Spacers High-Density Feature Formation Photo-lithographically defined sacrificial structures

15. FLCC 11/06/2006 Device 15 Y.-K. Choi et al., IEEE Trans. Electron Devices, Vol. 49, p. 436, 2002 Spacer vs. Resist Lithography Spacer lithography yields superior CD uniformity

16. FLCC 11/06/2006 Device 16 Gate Patterning using Spacer Lithography 1.Define fine-line features in a hard-mask layer using spacer lithography regular geometry (lines and spaces) L g <  pitch P ≤ 2.Pattern fine-line features (to remove hard-mask where gate lines are not desired) minimum feature size > P alignment tolerance = P  L g 3.Define large features in a resist layer using photolithography minimum feature size  P alignment tolerance >L g

17. FLCC 11/06/2006 Device 17 Spacer Gate Patterning Benefits Provides fine-line gate electrodes oriented in parallel and laid out on a regular grid –Minimizes feature variations for improved yield –Facilitates RET to achieve smallest possible feature sizes  tight control of L g  high parametric yield Note that the geometrically regular mask (Step 1) can be used for multiple chip designs, to save cost

18. FLCC 11/06/2006 Device 18 LgLg LgLg Gate formation by spacer lithography  uniform L g Achieving Uniform Gate Length Fin formation by conventional lithography  non-uniform L g Y.-K. Choi et al., IEDM Technical Digest, pp. 259-262, 2002

19. FLCC 11/06/2006 Device 19 Outline Introduction Spacer Lithography Device Simulation Study –Approach –Initial results Summary and Future Work

20. FLCC 11/06/2006 Device 20 Approach Use 3-D device simulations (Sentaurus Device) to investigate the benefits of spacer gate lithography –nominal L g < 40nm Sources of variation include: –L g variations –line-edge roughness (LER) –statistical dopant fluctuations (SDF)

21. FLCC 11/06/2006 Device 21 EUV Resist LER Data from AMD Average CD = 37.9nm Standard Deviation = 1.7nm

22. FLCC 11/06/2006 Device 22 RTA: 1000°C 10s Spike: 1100°C 1sFlash: 1300°C 1ms S/D ext. implant: 3E14 As + cm -2 @ 3keV Trend toward diffusion-less anneal  increased junction roughness Impact of S/D Implant Anneal Conditions

23. FLCC 11/06/2006 Device 23 Device Simulation: Methodology LER Generation Structure Generation Device Simulation W channel = 50nm L g = 37nm X j = 20.4nm T ox = 1.2nm N body = 2.2E18cm -3 Assume S/D junction follows LER profile. Sentaurus 3D Device simulation Collect statistical distributions of I ON and I OFF

24. FLCC 11/06/2006 Device 24 Simulated MOSFET Structures Resist LithographySpacer Lithography Plan View (gate electrode) Isometric ViewPlan View (gate electrode) Isometric View

25. FLCC 11/06/2006 Device 25 Initial Results Smaller spread in I OFF vs. I ON is seen for spacer gate lithography

26. FLCC 11/06/2006 Device 26 Outline Introduction Spacer Lithography Device Simulation Study Summary and Future Work

27. FLCC 11/06/2006 Device 27 Summary Tighter control of L g will be needed with transistor scaling; however, this becomes more difficult as the “sub-wavelength gap” increases Spacer lithography provides for better CD control, and will eventually be a more cost-effective approach than conventional resist lithography for patterning gate electrodes LER effects on MOSFET performance can be mitigated by spacer gate lithography Future Work Assess the relative impacts of various sources of variability (line-width variations, LER, SDF)