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Celltroy Technologies Cell Compiler “Ardon” Overview.

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Presentation on theme: "Celltroy Technologies Cell Compiler “Ardon” Overview."— Presentation transcript:

1 Celltroy Technologies Cell Compiler “Ardon” Overview

2 Problems in Standard Cell Libraries and UDSM  For UDSM technologies OPC and PSM create very complex context based design rules.  Cost of library development and design changes doubled in last 2 years.  Industry waste 10 bln $ on yield and hand-work changes (Design Yield Cost Model, ЕЕ Times 2005) 2

3 Problems in 65 nm and lower  Complex context based design rules made hand work very expensive.  Library variation: need several versions of the same cell based on usage context.  Design rule change imply cell redesign.  Need specialized automation tool for library designers. 3

4 4 Solution Netlist Design/Optimization Layout creation Parasitic Extraction Physical Verification Characterization View Generation QA Cosmos SE HSPICE Circuit Explorer Cadabra Star RCXT Hercules NanoChar HSPICE Virtuoso/Cosmos “Ardon”

5 5 Project Goals  Automation of activities related to standard cell library  Optimization  Leakage power  Yield improvement  Generation  Gridless and adaptive routing  Template based fast generation  Migration

6 6 Underlying technology  Multicriterion, multiparameter cell optimization (solution of dynamic programming problem)  Integrated simulation, LVS, DRC, RC Extraction, characterization,  Statistically optimized transistor placement  1.5D Compaction with DRC  Tool can be embedded in to existing flows  Tool can connect 3 rd party tools via plugin model

7 Competitors – Synopsys Cadabra  The main competitor with solid client base  Strengths  Automatic creation flow.  Semi-automatic migration flow  Weaknesses  Standalone tool provided as service. Need Circuit-Explorer, HSPICE, Hercules and Star-RCXT which makes him ~$1M tool.  Clients  Agere, Cypress, Delco, IBM, MIPS, National, Qualcomm, Vitesse, TI, Intel, Micron, HP, Rockwell, Cisco, ST, Analog Devices, Matushita, Toshiba, Sony, Sharp, Fujitsu, Renesas, TSMC, HuaJie, UMC, Hynix  Opportunities  Providing compatibility with the existing Cadabra projects format can push to try Ardon. 7

8 Competitor – Compactors  Compaction tools provide only the ability to migrate libraries  Sagantec (Dream and Hurricane)  Market leader in layout compaction  Virtuoso Layout Migrate  Former Q Design Automation (Q-Trek)  Strengths  Ability to migrate large designs up block/chip level  Weaknesses  Lower quality of layout due to of fast, generalized algorithms designed to shrink larger designs.  Limited to linear scaling, does not handle architecture changes.  If compaction does not meet design objectives, the fall-back is manual layout.  Opportunities  Customers who have libraries that require architectural changes.  Customers that have to create/recreate significant number of new cells.  Customers who require high quality of results 8

9 Competitor – 3 rd Party Libraries  3 rd party libraries obviate the need for a potential customer to develop a library in-house.  ARM (Artisan)  SAGE, SAGE-X, SAGE-HS, Metro. Can be purchased under per chip-royalties.  Virage  ASAP, ASAP metal programmable libraries  TSMC, Virtual Silicon  Strengths  Can eliminate upfront costs under a per-chip licensing model  Off-the-shelf availability  Weaknesses  “Free library” is more expensive in long run  Libraries are general purpose, not optimized for functions and drive strengths.  Library vendors can add custom cells, but it is expensive, lose control of IP.  Reduces ability to differentiate.  Opportunities  Customers can quickly create libraries that optimized for specific conditions (power, performance, speed, area, yield). Thus synthesis tools can produce better results if there is a richer library available. 9

10 Team  Moscow  4 Software engineers, 2 hardware engineers  Yerevan  5 Software engineers, 3 hardware engineers  Patent is being filed, 2 more expected.  Key members has 10 years of experience with EDA and software management. 10

11 Milestones  Leakage power optimization for UDSM technologies (DONE)  Yield optimization (28 Dec 2007)  Multicriterion optimization and visualization (28 Dec 2007)  Automatic generation (template based) (1 May 2008)  Handling whole library (DAC’2008)  Create 400 cell library with different drive-strengths (at least 200 need to have hand-made quality)  Support characterization  Do automatic datasheet generation  Support all-views  Need to be all-in-one. One tool covering all flow. 11


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