1. Sept. 2005EE37E Adv. Digital Electronics Lesson 1 (Part 2) FPGA Architectures

2. Sept. 2005EE37E Adv. Digital Electronics designs must be sent for expensive and time consuming fabrication in semiconductor foundry bought off the shelf and reconfigured by designers themselves Two competing implementation approaches ASIC Application Specific Integrated Circuit FPGA Field Programmable Gate Array designed all the way from behavioral description to physical layout no physical layout design; design ends with a bitstream used to configure a device

3. Sept. 2005EE37E Adv. Digital Electronics Which Way to Go? Off-the-shelf Low development cost Short time to market Reconfigurability High performance ASICsFPGAs Low power Low cost in high volumes

4. Sept. 2005EE37E Adv. Digital Electronics Major FPGA Vendors SRAM-based FPGAs Xilinx, Inc. Altera Corp. Atmel Lattice Semiconductor Flash & antifuse FPGAs Actel Corp. Quick Logic Corp.

5. Sept. 2005EE37E Adv. Digital Electronics Other FPGA Advantages Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower –Mistakes not detected at design time have large impact on development time and cost –FPGAs are perfect for rapid prototyping of digital circuits Easy upgrades like in case of software Unique applications –reconfigurable computing

6. Sept. 2005EE37E Adv. Digital Electronics We analyze here the basic structures of FPGAs, known as fabrics. There are different ways to build an FPGA. The two major styles of FPGAs are: SRAM- based and antifuse-based FPGAs. The features of I/O pins are fairly similar among these two types of FPGAs.

7. Sept. 2005EE37E Adv. Digital Electronics Characteristics of FPGA programming Technologies

8. Sept. 2005EE37E Adv. Digital Electronics 1-bit Static RAM

9. Sept. 2005EE37E Adv. Digital Electronics Elements of an FPGA fabric Logic Element (LE) or CLB Interconnect. I/O pins. … LE interconnect IOB …

10. Sept. 2005EE37E Adv. Digital Electronics Terminology Configuration: bits that determine logic function + interconnect. CLB: combinational logic block = logic element (LE) = Configurable Logic Block (correct meaning) LUT: Lookup table = SRAM used for truth table. I/O block (IOB): I/O pin + associated logic and electronics.

11. Sept. 2005EE37E Adv. Digital Electronics Fine-,Medium-,and Coarse-grained Architectures It’s common to categorize FPGA by analyzing the size and complexity of its internal logic elements. In a fine-grained architecture, each logic block can be used to implement only a very simple function. For example,it might be possible to configure the block to act as any 3-input function,such as: –a primitive logic gate (AND,OR,NAND,etc), – a storage element(DFF,D-Latch,etc) Today fine-grained architectures are being replace by medium- and coarse-grained, where each logic block contains a relative large amount of logic.

12. Sept. 2005EE37E Adv. Digital Electronics As the granularity of the blocks increases to medium-grained and higher, the amount of connections into the blocks decreases compared to the amount of functionality they can support. Today’s FPGAs are devices that have: –Embedded RAMs –Embedded multipliers, adders, and MACs (multiply accumulators) –Embedded Hard Processor Cores –Embedded Clock trees and clock managers

13. Sept. 2005EE37E Adv. Digital Electronics MUX- versus LUT-based Logic Blocks There are two fundamental incarnation of the programmable logic blocks used to form the medium-grained architectures referenced as: MUX based and LUT based.

14. Sept. 2005EE37E Adv. Digital Electronics MUX-based Quicklogic supports MUX-based architectures (www.quicklogic.com) MUX-based architectures have an advantage when it comes to implementing control logic along the lines of if..else

15. Sept. 2005EE37E Adv. Digital Electronics LUT-based LUT-architectures are the leaders in anything to do with arithmetic processing.

16. Sept. 2005EE37E Adv. Digital Electronics LUT versus distributed RAM versus SR The fact that the core of a LUT in a SRAM- based device comprises a number of RAM cells offers a number of interesting possibilities: –Configuration as lookup table –Configuration as small RAM block This is referred to as distributed RAM because (a) the LUTs are strewn (distributed) across the surface of the chip, and (b) this differentiates it from larger chunks of block RAM. Each LUT may be considered to be multifaceted.

17. Sept. 2005EE37E Adv. Digital Electronics A multifacetedLUT.

18. Sept. 2005EE37E Adv. Digital Electronics CLBs (Xilinx) and LABs (Altera) The core building block in a modern FPGA from Xilinx is called a logic cell (LC). An LC comprises: –a 4-inputLUTwhich can also acts as a 16 x 1 RAM or a 16-bit shift register, –a multiplexer, –and a register. The equivalent core building block in an FPGA from Altera is called a logic element (LE).

19. Sept. 2005EE37E Adv. Digital Electronics A simplified view of a Xilinx LC

20. Sept. 2005EE37E Adv. Digital Electronics Altera’s Logic Element Each Logic Element (LE) contains the following: A 16-bit SRAM lookup table (LUT) – this can implement an arbitrary 4- input logic function (as truth table). Circuitry that form fast carry chain and fast cascade chain (see later). A D-register that can be by-passed. Various preset/reset logic for the register.

21. Sept. 2005EE37E Adv. Digital Electronics The next step up the hierarchy is what Xilinx calls a slice:

22. Sept. 2005EE37E Adv. Digital Electronics Moving one more level up the hierarchy, we come to what Xilinx calls a configurable logic block (CLB) and what Altera refers to as a logic array block (LAB). A CLB Containing four slices (the number of slices depends on the FPGA family).

23. Sept. 2005EE37E Adv. Digital Electronics Programmable wiring Organized into channels. –Many wires per channel. Connections between wires made at programmable interconnection points. Must choose: –Channels from source to destination. –Wires within the channels.

24. Sept. 2005EE37E Adv. Digital Electronics Programmable interconnection point DQ An interconnection point controlled by an SRAM cell When the transistor’s gate is high, the transistor conducts and connects the two wires. Logic elements must be interconnected to implement complex machines. An SRAM-based FPGA uses SRAAM to hold the information used to program the interconnect. MOS Transistor

25. Sept. 2005EE37E Adv. Digital Electronics Programmable wiring paths

26. Sept. 2005EE37E Adv. Digital Electronics Choosing a path LE

27. Sept. 2005EE37E Adv. Digital Electronics Routing problems Global routing: –Which combination of channels? Local routing: –Which wire in each channel? Routing metrics: –Net length. –Delay.

28. Sept. 2005EE37E Adv. Digital Electronics I/O Fundamental selection: input, output, three- state? Additional features: –Register. –Voltage levels. –Slew rate.

29. Sept. 2005EE37E Adv. Digital Electronics Configuration Must set control bits for: –LE. –Interconnect. –I/O blocks. Usually configured off-line. –Separate burn-in step (antifuse). –At power-up (SRAM).

30. Sept. 2005EE37E Adv. Digital Electronics Configuration vs. programming FPGA configuration: –Bits stay at the device they program. –A configuration bit controls a switch or a logic bit. CPU programming: –Instructions are fetched from a memory. –Instructions select complex operations. CPUmemory add r1, r2IRadd r1, r2

31. Sept. 2005EE37E Adv. Digital Electronics Xilinx  Primary products: FPGAs and the associated CAD software  Main headquarters in San Jose, CA  Fabless* Semiconductor and Software Company  UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}  Seiko Epson (Japan)  TSMC (Taiwan ) Programmable Logic Devices ISE Alliance and Foundation Series Design Software

32. Sept. 2005EE37E Adv. Digital Electronics Xilinx FPGA Families Old families –XC3000, XC4000, XC5200 –Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. High-performance families –Virtex (0.22µm) –Virtex-E, Virtex-EM (0.18µm) –Virtex-II, Virtex-II PRO (0.13µm) Low Cost Family –Spartan/XL – derived from XC4000 –Spartan-II – derived from Virtex –Spartan-IIE – derived from Virtex-E –Spartan-3

33. Sept. 2005EE37E Adv. Digital Electronics (Adapted from EE449,George Mason University)

34. Sept. 2005EE37E Adv. Digital Electronics Basic Spartan-II FPGA Block Diagram

35. Sept. 2005EE37E Adv. Digital Electronics CLB Structure Each slice has 2 LUT-FF pairs with associated carry logic Two 3-state buffers (BUFT) associated with each CLB, accessible by all CLB outputs

36. Sept. 2005EE37E Adv. Digital Electronics CLB Slice Structure Each slice contains two sets of the following: –Four-input LUT Any 4-input logic function, or 16-bit x 1 sync RAM or 16-bit shift register –Carry & Control Fast arithmetic logic Multiplier logic Multiplexer logic –Storage element Latch or flip-flop Set and reset True or inverted inputs Sync. or async. control

37. Sept. 2005EE37E Adv. Digital Electronics RAM16X1S O D WE WCLK A0 A1 A2 A3 RAM32X1S O D WE WCLK A0 A1 A2 A3 A4 RAM16X2S O1 D0 WE WCLK A0 A1 A2 A3 D1 O0 = = LUT or LUT RAM16X1D SPO D WE WCLK A0 A1 A2 A3 DPRA0DPO DPRA1 DPRA2 DPRA3 or Distributed RAM CLB LUT configurable as Distributed RAM –A LUT equals 16x1 RAM –Implements Single and Dual- Ports –Cascade LUTs to increase RAM size Synchronous write Synchronous/Asynchronous read –Accompanying flip-flops used for synchronous read

38. Sept. 2005EE37E Adv. Digital Electronics DQ CE DQ DQ DQ LUT IN CE CLK DEPTH[3:0] OUT LUT = Shift Register Each LUT can be configured as shift register –Serial in, serial out Dynamically addressable delay up to 16 cycles For programmable pipeline Cascade for greater cycle delays Use CLB flip-flops to add depth

39. Sept. 2005EE37E Adv. Digital Electronics Shift Register Register-rich FPGA –Allows for addition of pipeline stages to increase throughput Data paths must be balanced to keep desired functionality 64 Operation A 4 Cycles8 Cycles Operation B 3 Cycles Operation C 64 12 Cycles 3 Cycles 9-Cycle imbalance

40. Sept. 2005EE37E Adv. Digital Electronics COUT D Q CK S R EC D Q CK R EC O G4 G3 G2 G1 Look-Up Table Carry & Control Logic O YB Y F4 F3 F2 F1 XB X Look-Up Table F5IN BY SR S Carry & Control Logic CIN CLK CE SLICE Carry & Control Logic

41. Sept. 2005EE37E Adv. Digital Electronics  Each CLB contains separate logic and routing for the fast generation of sum & carry signals –Increases efficiency and performance of adders, subtractors, accumulators, comparators, and counters  Carry logic is independent of normal logic and routing resources Fast Carry Logic LSB MSB Carry Logic Routing

42. Sept. 2005EE37E Adv. Digital Electronics Accessing Carry Logic  All major synthesis tools can infer carry logic for arithmetic functions –Addition (SUM <= A + B) –Subtraction (DIFF <= A - B) –Comparators (if A < B then…) –Counters (count <= count +1)

43. Sept. 2005EE37E Adv. Digital Electronics Block RAM Spartan-II True Dual-Port Block RAM Port A Port B Block RAM Most efficient memory implementation –Dedicated blocks of memory Ideal for most memory requirements –4 to 14 memory blocks 4096 bits per blocks –Use multiple blocks for larger memories Builds both single and true dual-port RAMs

44. Sept. 2005EE37E Adv. Digital Electronics Spartan-II Block RAM Amounts

45. Sept. 2005EE37E Adv. Digital Electronics Block RAM Port Aspect Ratios 0 4095 1 1023 4 0 1047 2 0 511 8 0 255 16 0 4k x 1 2k x 2 1k x 4 512 x 8 256 x 16

46. Sept. 2005EE37E Adv. Digital Electronics Basic I/O Block Structure D EC Q SR D EC Q SR D EC Q SR Three-State Control Output Path Input Path Three-State Output Clock Set/Reset Direct Input Registered Input FF Enable

47. Sept. 2005EE37E Adv. Digital Electronics IOB Functionality IOB provides interface between the package pins and CLBs Each IOB can work as uni- or bi-directional I/O Outputs can be forced into High Impedance Inputs and outputs can be registered –advised for high-performance I/O Inputs can be delayed

48. Sept. 2005EE37E Adv. Digital Electronics Routing Resources PSM CLB PSM CLB Programmable Switch Matrix

49. Sept. 2005EE37E Adv. Digital Electronics Spartan-II FPGA Family Members

50. Sept. 2005EE37E Adv. Digital Electronics

51. Sept. 2005EE37E Adv. Digital Electronics Virtex-II 1.5V Architecture C onfigurable L ogic B lock Block RAMs I / O B lock Multipliers 18 x 18 Block RAMs Multipliers 18 x 18 Block RAMs Multipliers 18 x 18 Block RAMs Multipliers 18 x 18

52. Sept. 2005EE37E Adv. Digital Electronics Virtex-II 1.5V DeviceCLB Array SlicesMaximum I/O BlockRAM (18kb) Multiplier Blocks Distributed RAM bits XC2V408x825688448,192 XC2V8016x85121208816,384 XC2V25024x161,53620024 49,152 XC2V50032x243,07226432 98,304 XC2V100040x325,12043240 163,840 XC2V150048x407,68052848 245,760 XC2V200056x4810,75262456 344,064 XC2V300064x5614,33672096 458,752 XC2V400080x7223,040912120 737,280 XC2V600096x8833,7921,104144 1,081,344 XC2V8000112x10446,5921,108168 1,490,944

53. Sept. 2005EE37E Adv. Digital Electronics Virtex-II Block SelectRAM Virtex-II BRAM is 18 kbits –Additional “parity” bits available in selected configurations WidthDepthAddressDataParity 116,386[13:0][0]N/A 28,192[12:0][1:0]N/A 44,096[11:0][3:0]N/A 92,048[10:0][7:0][0] 181,024[9:0][15:0][1:0] 36512[8:0][31:0][3:0]

54. Sept. 2005EE37E Adv. Digital Electronics FPGA Nomenclature

55. Sept. 2005EE37E Adv. Digital Electronics Design Methods and Tools

56. Sept. 2005EE37E Adv. Digital Electronics Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis

57. Sept. 2005EE37E Adv. Digital Electronics Design process (2) Implementation Configuration Timing simulation On chip testing

58. Sept. 2005EE37E Adv. Digital Electronics Design Process control from Active-HDL

59. Sept. 2005EE37E Adv. Digital Electronics Simulation Tools Many others…

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61. Sept. 2005EE37E Adv. Digital Electronics

62. Sept. 2005EE37E Adv. Digital Electronics Synthesis Tools … and others

63. Sept. 2005EE37E Adv. Digital Electronics architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW; VHDL description Circuit netlist Logic Synthesis

64. Sept. 2005EE37E Adv. Digital Electronics Features of synthesis tools Interpret RTL code Produce synthesized circuit netlist in a standard EDIF format Give preliminary performance estimates Some can display circuit schematics corresponding to EDIF netlist

65. Sept. 2005EE37E Adv. Digital Electronics Implementation After synthesis the entire implementation process is performed by FPGA vendor tools

66. Sept. 2005EE37E Adv. Digital Electronics

67. Sept. 2005EE37E Adv. Digital Electronics Translation UCF NGD EDIF NCF Native Generic Database file Constraint Editor User Constraint File Native Constraint File Electronic Design Interchange Format Circuit netlistTiming Constraints Synthesis

68. Sept. 2005EE37E Adv. Digital Electronics Sample UCF File # # Constraints generated by Synplify Pro 7.3.3, Build 039R # # Period Constraints #Begin clock constraints #End clock constraints # Output Constraints # Input Constraints # Location Constraints # End of generated constraints NET "clock" LOC = "P88"; NET "control(0)" LOC = "P50"; NET "control(1)" LOC = "P48"; NET "control(2)" LOC = "P42"; NET "reset" LOC = "P93"; NET "segments(0)" LOC = "P67"; NET "segments(1)" LOC = "P39"; NET "segments(2)" LOC = "P62"; NET "segments(3)" LOC = "P60"; NET "segments(4)" LOC = "P46"; NET "segments(5)" LOC = "P57"; NET "segments(6)" LOC = "P49";

69. Sept. 2005EE37E Adv. Digital Electronics Pin Assignment Lab CLOCK CONTROL(0) CONTROL(2) CONTROL(1) RESET SEGMENTS(0) SEGMENTS(1) SEGMENTS(2) SEGMENTS(3) SEGMENTS(4) SEGMENTS(5) SEGMENTS(6) P39 P42 P46 P48 P49 P50 P57 P60 P62 P67 P88 P93 FPGA

70. Sept. 2005EE37E Adv. Digital Electronics Parallel Port Interface

71. Sept. 2005EE37E Adv. Digital Electronics Constraints Editor

72. Sept. 2005EE37E Adv. Digital Electronics Circuit netlist

73. Sept. 2005EE37E Adv. Digital Electronics Mapping LUT2 LUT3 LUT4 LUT5 LUT1 FF1 FF2

74. Sept. 2005EE37E Adv. Digital Electronics Placing CLB SLICES FPGA

75. Sept. 2005EE37E Adv. Digital Electronics Routing Programmable Connections FPGA

76. Sept. 2005EE37E Adv. Digital Electronics Static Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency

77. Sept. 2005EE37E Adv. Digital Electronics Static Timing Analysis Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers DQ in clk DQ out t P logic t Critical = t P FF + t P logic + t S FF

78. Sept. 2005EE37E Adv. Digital Electronics Static Timing Analysis Min. Clock Period = Length of The Critical Path Max. Clock Frequency = 1 / Min. Clock Period

79. Sept. 2005EE37E Adv. Digital Electronics Configuration Once a design is implemented, you must create a file that the FPGA can understand –This file is called a bit stream: a BIT file (.bit extension) The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information

80. Sept. 2005EE37E Adv. Digital Electronics Resources & Required Reading Spartan FPGA devices Xilinx Spartan-II 2.5V FPGA Family: Complete Data Sheet Module 1: Introduction & Ordering Information Module 2: Functional Description http://direct.xilinx.com/bvdocs/publications/ds001.pdf

81. Sept. 2005EE37E Adv. Digital Electronics Integrated Interfaces: Active-HDL with Synplify® http://www.aldec.com/Previews/active_synplify.htm Integrated Synthesis and Implementation http://www.aldec.com/Previews/synthesis_implementation.htm Resources & Required Reading FPGA Tools