1. High Speed Analog to Digital Converter
Presentation by :
Abdelrahman Radwan
George Ekladious

2. Introduction
An electronic integrated circuit which transforms a signal from analog (continuous) to digital (discrete) form.
Analog signals are directly measurable quantities.
Digital signals only have two states. For digital computer, we refer to binary states, 0 and 1.

3. Why ADC ? storing analog data
replicating or reconstructing analog data
Microprocessors can only perform complex processing on digitized signals.
When signals are in digital form they are less susceptible to the deleterious effects of additive noise.

4. ADC Applications Measurements / Data Acquisition Control Systems
PLCs (Programmable Logic Controllers)
Sensor integration (Robotics)
Cell Phones
Video Devices
Audio Devices t e e*
Controller
0010
0101
0011
1011 ∆t
e*(∆t)
1001
1010
u*(∆t)

5. Principal of Operation

6. ADC Process
Sampling and Holding (S/H)
Quantizing and Encoding (Q/E)

7. Holding and Sampling Holding signal benefits the
accuracy of the A/D conversion.
Minimum sampling rate
should be at least twice
the highest data frequency
of the analog signal.

8. Quantizing - breaking down analog value is a set of finite states.
Encoding - assigning a digital word or number to each state and matching it to the input signal

9. Resolution: The smallest change in analog signal that will result in a change in the digital output.
V = Reference voltage range N = Number of bits in digital output. 2N = Number of states. ∆V = Resolution
The resolution represents the quantization error inherent in the conversion of the signal to digital form

10. Quantizing
The number of possible states that the converter can output is: N=2n where n is the number of bits in the AD converter Example: For a 3 bit A/D converter, N=23=8. Analog quantization size: Q=(Vmax-Vmin)/N = (10V – 0V)/8 = 1.25V

11. Quantization
We have 0-10V signals. Separate them into a set of discrete states with 1.25V increments.

12. Encoding Here we assign the digital value
(binary number) to each state
for the computer to read.

13. Accuracy of A/D Conversion
There are two ways to best improve the accuracy of A/D conversion:
increasing the resolution which improves the accuracy in measuring the amplitude of the analog signal.
increasing the sampling rate which increases the maximum frequency that can be measured.

14. Sampling Rate
Frequency at which ADC evaluates analog signal. As we see in the second picture, evaluating the signal more often more accurately depicts the ADC signal.

15. Aliasing
Occurs when the input signal is changing much faster than the sample rate.
For example, a 2 kHz sine wave being sampled at 1.5 kHz would be reconstructed as a 500 Hz (the aliased signal) sine wave.
Nyquist Rule:
Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing.

16. A/D converter Types Flash ADC Delta-Sigma ADC
Dual Slope (integrating) ADC
Successive Approximation ADC

17. Flash ADC
Uses the 2N resistors to form a ladder voltage divider, which divides the reference voltage into 2N equal intervals.
Consists of a series of comparators, each one comparing the input signal to a unique reference voltage.
The comparator outputs connect to the inputs of a priority encoder circuit, which produces a binary output

18. Flash ADC Circuit

19. Comparator If Output VIN > VREF High VIN < VREF Low VIN + VOUT -

20. Flash ADC operation
As the analog input voltage exceeds the reference voltage at each comparator, the comparator outputs will sequentially saturate to a high state.
The priority encoder generates a binary number based on the highest-order active input, ignoring all other active inputs.

21. Example Design a Flash ADC with the following parameters:
number of output bits = 2;
input voltage range = 0 to 3V;
comparator outputs have positive saturation = +12V and negative saturation = 0V;

22. Solution
Resolution = input voltage range / 2n = 3 / 22 = 0.75V Number of Comparators : 2n = 22 = 4 Thus we need 4 comparators and 4 equal resistors.

23. Solution continued
Vref= 3V

24. Solution continued

25. Flash ADC Advantages and Disadvantages
Very Fast .
Very simple operational theory .
Speed is only limited by gate and comparator propagation delay .
Disadvantages:
Expensive.
Each additional bit of resolution requires twice the comparators.
Prone to produce glitches in the output

26. Successive Approximation ADC

27. Operation Principle
A Successive Approximation Register (SAR) is added to the circuit
Instead of counting up in binary sequence, this register counts by trying all values of bits starting with the MSB and finishing at the LSB.
The register monitors the comparators output to see if the binary count is greater or less than the analog signal input and adjusts the bits accordingly

28. Advantages and Disadvantages SA ADC
Capable of high speed and reliable .
Medium accuracy compared to other ADC types.
Good tradeoff between speed and cost.
Disadvantages :
Higher resolution successive approximation ADC’s will be slower

29. Successive Approximation ADC Example
Goal: Find digital value Vin
8-bit ADC
Vin = 7.65
Vfull scale = 10

30. Successive Approximation ADC Example
Vfull scale = 10, Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 7
(Vfull scale +0)/2 = 5
7.65 > 5  Bit 7 = 1 1

31. Successive Approximation ADC Example
Vfull scale = 10, Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 6
(Vfull scale +5)/2 = 7.5
7.65 > 7.5  Bit 6 = 1 1  1

32. Successive Approximation ADC Example
Vfull scale = 10, Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 5
(Vfull scale +7.5)/2 = 8.75
7.65 <  Bit 5 = 0 1  1  0

33. Successive Approximation ADC Example
Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 4
( )/2 = 8.125
7.65 <  Bit 4 = 0 1  1  0

34. Successive Approximation ADC Example
Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 3
( )/2 =
7.65 <  Bit 3 = 0 1  1  0 0 

35. Successive Approximation ADC Example
Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 2
( )/2 =
7.65 <  Bit 2 = 0 1  1  0 0 

36. Successive Approximation ADC Example
Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 1
( )/2 =
7.65 >  Bit 1 = 1 1  1  0 0  1 

37. Successive Approximation ADC Example
Vin = 7.65
MSB  LSB
Average high/low limits
Compare to Vin
Vin > Average  MSB = 1
Vin < Average  MSB = 0
Bit 0
( )/2 =
7.65 >  Bit 0 = 1 1  1  0 0  1 

38. Wilkinson Analog Digital Converter (ADC) circuit schematic diagram
Wilkinson ADC
Wilkinson Analog Digital Converter (ADC) circuit schematic diagram
Speed: High
Cost: High
Accuracy: High

39. ADC Types Comparaison

40. Why High speed ADCs ?
Better Resolution Bandwidth Low Power

41. Better Resolution Bandwidth
The average speed of high-speed A/D converters has increased by a factor of ten over the past five years.

42. Low Power
The usage of portable devices such as laptops and Bluetooth devices its demanded to use a very low power ADC .

43. Current Research
14 GSps, four-bit data converter pair in 90 nm CMOS [7] .
The experimental results show that the The ADC consume 214 mW and from a 1.0-V supply and occupy mm2 .

44. Ultralow-Voltage High-Speed ADC
In the proposed design strategy [6], a 7-bit flash ADC is designed and fabricated in 90-nm CMOS to operate with a 0.5 V supply voltage.
Using two-way interleaving, the prototype achieves a maximum conversion rate of 420 MS/s with an ERBW of 50 MHz.
The total power consumption of the interleaved ADC is 4.1 mW.
Using the proposed FD-oriented design, this paper achieves at least 3.5 times speed enhancement compared with other state-of-the-art ULV ADC

45. High Speed ADCs Comparison

46. References http://ume.gatech.edu/mechatronics_course/ADC_F05.ppt
MS320LF2407A_Documents/Intro-ADC.pdf
Lin, J.; Mano, I.; Miyahara, M.; Matsuzawa, A., "Ultralow- Voltage High-Speed Flash ADC Design Strategy Based on FoM- Delay Product," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.PP, no.99, pp.1,1
Hao-Chiao Hong; Yung-Shun Chen; Wei-Chieh Fang, "14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.22, no.6, pp.1238,1247, June 2014