1. Crosstalk Noise Optimization by Post-Layout Transistor Sizing Masanori Hashimoto Masao Takahashi Hidetoshi Onodera Dept. CCE, Kyoto University

2. 2 Post-Layout Tr. Sizing for Crosstalk Noise Reduction Overview Crosstalk noise depends on coupling length coupling position driver strength of aggressor hold strength of victim Routing & interconnect optimization Our target Use analytic noise model suitable for a lot of repetitive noise estimation Optimize Tr. sizes preserving interconnects no iterations between Tr. sizing and layout

3. 3 Post-Layout Tr. Sizing for Crosstalk Noise Reduction Features Downsize too strong drivers continuous sizing vary PN ratio consider noise margin and transition time constraints Optimization with interconnect preservation no iterations between layout and Tr. sizing accurately-extracted coupling information

4. 4 On-Demand Cell Layout Generation(VARDS) Same height Normal size Half size Shrink Tr. width Terminals are fixed.

5. 5 Contents Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion

6. 6 Generic RC Trees on LSI victim aggressor 1 aggressor 3 aggressor 2 branch 1 branch 2 Multiple aggressors, multiple branches

7. 7 Noise estimation for two partially-coupled interconnects closed-form noise waveform Multiple aggressors superpose noises from each aggressor Multiple sinks transform into two partially-coupled interconnects Crosstalk Noise Estimation Overview Aggressor Victim

8. 8 Modeling of Two Partially- Coupled Interconnects V noise (t) victim model aggressor model V agg (t)

9. 9 Noise Waveform and Peak Noise Voltage Rv1Rv2Rv3 Cv1 Cv2Cv3 Cc Vagg Vnoise peak noise noise waveform

10. 10 Multiple Aggressors victim aggressor 1 aggressor n V noise 1 (t) aggressor n V noise n (t) aggressor 1 V noise (t) V noise (t)=V noise 1 (t)+ ・・・ +V noise n (t) Superposition

11. 11 Superposition Considering Timing Window fastest arrival time  t  latest arrival time other Superposition of peak noise (timing window) Timing window calculation Fastest arrival time: STA with coupling cap. multiplied by -1 Latest arrival time: STA with coupling cap. multiplied by 3 [P. Chen, et.al., ICCAD2000] Eliminate pessimistic estimation using timing window

12. 12 Contents Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion

13. 13 Optimization Algorithm in Each Victim Net Downsize Tr. Select agg. net with max-priority from non-optimized net. Downsize Tr. such that V a 2 +V v 2 is minimum. Finish? All aggressors are optimized? Noise is smaller than V target ? Calculate priority i Downsize Tr. Finish ？ Y N start end timing marginnoise voltage victim aggressor High priority strong impact and loose timing constraint downsize Consider both noises at aggressor and victim

14. 14 Overall Optimization Algorithm Put nets into L Put nets(> threshold ・ V max ) into list L. Execute local opt. Optimize net with max-noise in L. threshold ・ V max is target value V target. Finish? L is empty? Calculate noise Execute local opt. Finish ？ Y N start end Put nets into L Execute several times, decreasing threshold. 1 threshold 0 Peak noise reduction Most of nets are optimized. Global optimality

15. 15 Contents Crosstalk noise estimation Noise optimization algorithm Experimental results Conclusion

16. 16 Experimental Conditions 0.35  m technology Two combinational circuits designed for minimizing delay dsp_alu: 2.3x2.3mm 2, 13k cells des: 0.8x0.8mm 2, 3k cells RC extraction Small coupling caps.(<10fF) are treated as caps. to ground. Supply voltage: 3.3V Cell height: 13 routing pitches Tr. Width: 6.2  m(standard), 0.9  m(minimum)

17. 17 Optimization Results of Crosstalk Noise Reduction descircuitdsp_alu 0.40 -> 0.19peak noise[V]1.00 -> 0.50 12CPU time[s]604 3.4k#cells13k Optimize noise without delay increase

18. 18 Initial and Optimized Layouts Initial Optimized

19. 19 Accuracy of Peak Noise Estimation Average error: 10mV All coupled interconnects in des circuit Actual interconnects with branches driven by CMOS gates

20. 20 Conclusion Propose crosstalk noise reduction method by post-layout Tr. sizing use analytic noise model downsize too strong aggressors preserve interconnects completely reduce peak noise by 50%