1. © 2002 ® Wireless Solution Update Asif Batada Marketing Manager, Wireless Business Unit Asif Batada Marketing Manager, Wireless Business Unit

2. © 2002 ® Agenda Mobile Base-station Architecture Basics of Digital IF and Digital Predistortion Linearizer RF Card Architecture Predistortion Linearizer Implementation Conclusion

3. © 2002 ® Antenna RNC I/F IP Interface Switch Controller A/D D/A Base Band Signal Processing Switch I/F Host Processor (CPU) Clock Generator PLD Application Control Board Channel Card RNC Digital IF Digital Predistortion Linearizer Mux/ De-Mux Host uP RF Card Base-Station Architecture LVDS w/CDR ATM proc PA LNA

4. © 2002 ® Agenda Mobile Base-station Architecture Basics of Digital IF and Digital Predistortion Linearizer RF Card Architecture Predistortion Linearizer Implementation Conclusion

5. © 2002 ® Digital IF Opportunity Digital IF is a high volume application for FPGA:  Macro BTS can be configured into two different ways: 2 carriers for 3 sectors 1 carrier for 6 sectors  Each BTS has Digital IF Implementation: 6 x EP1S20 Predistortion Implementation: 6 x EP1S10  6 x EP1S20 + 6 x EP1S10 per BTS 1 carrier (5Mhz for UMTS) 6 Sector Cell 60  3 Sector Cell 120 

6. © 2002 ® Traditional IF-Based Transmitter Issues with traditional transmitter  Not flexible to support multiple standards  Non-ideal local frequencies are source of noise  RF and analog components of radio are more difficult to manufacture and have higher reliability issues  Higher cost BB filter + 90º f1f1 IF filter RF filter f2f2 AmpPA I Q DAC

7. © 2002 ® Digital IF Sym. Mapper FIR filter NCO  FIR filter f2f2 AmpPA IF filter RF filter Digital Up-Converter With the advancement of data converter technology (100Msps +), it is possible to sample at IF (intermediate frequency) and do Channelization in Digital domain Advantages of Digital IF  Channel selection can be done in digital domain  Higher precision in frequency selection and shorter settling time of DDS  Good amplitude and phase balance  Extremely linear phase and very low shape factor of base-band filter DAC

8. © 2002 ® Predistortion Linearizer RF stage (transmitter) uses a linear Power Amplifier (PA) to boost the signals Linear PAs are very expensive  Some cases it makes up half the cost of BTS Non-Linear PAs are cheaper  LDMOS based technology  LDMOS introduces distortion of its own Predistortion in digital domain  Pre-distort the signal so that when it goes thru PA, the overall response is linear  Common technique – Look-up Table based approach Store the points on the transfer function in a look-up table One of our customers evaluating 20K400E for this application Nios is well suited Input Power Output Power Add Predistortion

9. © 2002 ® Agenda Mobile Base-station Architecture Basics of Digital IF and Digital Predistortion Linearizer RF Card Architecture Predistortion Linearizer Implementation Conclusion

10. © 2002 ® RF Card – 1 st Generation Design Customers have either designed their own Digital IF chip (w/o DPD) or are using ASSP (mostly GrayChip) Limitations with current implementation:  Custom Filter Specs – Adj Channel Power Ratio (ACPR) – Requirement Driven by Architecture  Decimation and Interpolation Ratios – Driven by Standards and Internal implementation Need to add more carriers  Availability of Multi-Carrier Power Amplifier  Higher capacity channel cards Higher Data rates over the back plane

11. © 2002 ® Interpolation RRC Filter   ResamplerDecimation RRC Filter ResamplerDecimation NCO Q Q ADC DAC To Ant From Ant To Channel Card (LVDS w/CDR) Input Fmt & Gain Cntrl From Ch. Card (LVDS w/ CDR) NCO RF Card I I I I Q Q Delay Matching Table Address Calc (I 2 +Q 2 ) 1/2 LUT (I & Q) Compare & Estimate RS Adaptive Est. I & Q Demod FFT Loop Delay Est From PA

12. © 2002 ® Agenda Mobile Base-station Architecture Basics of Digital IF and Digital Predistortion Linearizer RF Card Architecture Predistortion Linearizer Implementation Conclusion

13. © 2002 ® Delay Matching LUT (I & Q) ~100 entries 12 bit Wordlength Table Address Calc (I 2 +Q 2 ) 1/2 I Q Compare & Estimate RS I & Q Demodulator FFT Adaptive Est. Loop Delay Estimator Embedded Processor Altera MegaCore IP To DUC IQ - - I Q Altera Solution for DPD

14. © 2002 ® Optional FIFO, Memory, Other Logic Nios Processor Integer Mult / Complex Mult Example ALU Only ALU + Intgr Mult ALU + Cmplx Mult Loop Time (us) 11.1900.5600.011 Loop Clocks 1119561.1 MUL Clocks2533- Complex Mults per Second 89K1.8M90.9M Loop Time = Execution of a single complex multiply Loop Clocks = Number of clocks to execute single iteration MUL Clocks = Number of clocks to execute the MUL only Custom Instruction Example Hardware Accelerator x 50

15. © 2002 ® Flow Address Calculation DDC FFT Delay Matching (.) __ Gain (.) __ Gain V error  = tan -1 (.) S n+1 =S n -  *e scale R n+1 =R n -  *e rotate S n+1 =S n -  *e scale R n+1 =R n -  *e rotate I1I1 Q1Q1 InIn QnQn........ I1I1 Q1Q1 InIn QnQn........ I/P to DPD From PA Update LUT Loop Delay Meas H/W Accelerator Cmplx Mult Programmable Logic Implementation Software Implementation (Nios)

16. © 2002 ® Interpolation RRC Filter   Decimation RRC Filter ResamplerDecimation NCO Q To Ant From Ant To Channel Card (LVDS w/CDR) Input Fmt & Gain Cntrl From Ch. Card (LVDS w/ CDR) NCO RF Card – Comprehensive Solution I I Q Delay Matching Table Address Calc (I 2 +Q 2 ) 1/2 LUT (I & Q) Compare & Estimate RS Adaptive Est. I & Q Demod FFT Loop Delay Est From PA Arctan Resampler Altera MegaCore IP Stratix Tri-Matrix Stratix MAC Block H/W Accelerator

17. © 2002 ® Advantages of Using FPGA Greater Flexibility  Filter specification based on ACPR requirements  Optimal filter architecture for most efficient implementation  Support multi-mode capability Implement Optimal Number of Carriers and Standards Higher levels of integration  Integration of DPD, Digital IF and Transceivers  Saving board space  Cost savings Cost Effective Solution  Sub $40 in FPGA; Sub-$20 in HardCopy Speed and size improvements in FPGA can be easily leveraged to support more channels

18. © 2002 ® Conclusion RF portion of base-station going through revision Digital Predistortion Linearizer is a key functionality being added FPGA implementation offer significant advantage over ASSP implementation Altera Offers comprehensive solution including devices, tools and IP