1. CAS-FEST 2010 © E. Maricau, K.U. Leuven 1 Computer Aided Analog Circuit Design for Reliability Elie Maricau and Georges Gielen ESAT–MICAS K.U.Leuven, Belgium emaricau@esat.kuleuven.be

2. CAS-FEST 2010 © E. Maricau, K.U. Leuven 2 Contents  Introduction  Reliability Effect Modeling  Reliability Simulation  Reliability-aware Design  Conclusions

3. CAS-FEST 2010 © E. Maricau, K.U. Leuven 3 Towards Systems-on-Chip (SoC) Move to increased levels of integration  reduced cost, size/volume, power  improved performance Increasing chip complexity  integrated heterogeneous systems mixed hardware/software mixed RF/analog/digital [Staszewski, ISSCC ‘08]

4. CAS-FEST 2010 © E. Maricau, K.U. Leuven 4 Scaling to atomistic scale devices… Nanometer CMOS scaling problems:  Noise problems (signal integrity)  Leakage (digital)  Channel length modulation  Velocity saturation  Mobility degradation  Drain induced barrier lowering (DIBL)  Parasitic effects  IC reliability  … [ITRS 09]

5. CAS-FEST 2010 © E. Maricau, K.U. Leuven 5 IC Reliability …  Spatial Unreliability manufacturing process variations random defects [Chandra IOLTS 09]

6. CAS-FEST 2010 © E. Maricau, K.U. Leuven 6  the IC manufacturing suffers from defects and from inherent fluctuations results in faulty chips and in fluctuations in circuit performances yield smaller than 100% affects profitability of IC manufacturing process Spatial Unreliability [Bernstein, IBM Journal 06]

7. CAS-FEST 2010 © E. Maricau, K.U. Leuven 7 IC Reliability …  Spatial Unreliability manufacturing process variations random defects  Dynamic Unreliability workload dependent temperature variations EMC [Chandra IOLTS 09]

8. CAS-FEST 2010 © E. Maricau, K.U. Leuven 8 Dynamic Unreliability  Power, Voltage, Temperature variations EMC EOS ESD …

9. CAS-FEST 2010 © E. Maricau, K.U. Leuven 9 IC Reliability …  Spatial Unreliability manufacturing process variations random defects  Dynamic Unreliability workload dependent temperature variations EMC  Temporal Unreliability ageing effects [Chandra IOLTS 09]

10. CAS-FEST 2010 © E. Maricau, K.U. Leuven 10 Temporal Unreliability  IC level Electro migration Stress voiding Bias Temperature Instability (BTI) Hot Carrier Injection (HCI) Time Dependent Dielectric Breakdown (TDDB)...  PCB Corrosion Solder cracking...  Packaging Bond wire sheering...

11. CAS-FEST 2010 © E. Maricau, K.U. Leuven 11 Reliability Assessment  Device Level Accelerated stress tests on individual devices Device failure criterion is chosen arbitrarily (e.g.  V TH >50mV)  Circuit Level Test for Reliability (TFR) » e.g. screening, life test, burn-in,… Design for Reliability (DFR) » Transistor aging models » Reliability simulation tools DFR TFR

12. CAS-FEST 2010 © E. Maricau, K.U. Leuven 12 Contents  Introduction  Reliability Effect Modeling  Reliability Simulation  Reliability-aware Design  Conclusions

13. CAS-FEST 2010 © E. Maricau, K.U. Leuven 13 What do we need?  Compact models for all important unreliability effects Include all important factors » e.g. W,L, Vgs, Vds, T, … Include interaction effects » e.g. Vds-Vgs for HCI Cover a broad range of factor values » e.g. Vgs = [0V … 1.5V], W=[0.08  m-10  m] Model time-varying stress effects » e.g. Vgs(t)= VGS + sin(0.5,1e6)

14. CAS-FEST 2010 © E. Maricau, K.U. Leuven 14 Reliability in Nanometer CMOS  Process variability  Hot Carrier Degradation  NBTI (PBTI)  Time Dependent Dielectric Breakdown n+n+ n+n+ [ITRS 2009]

15. CAS-FEST 2010 © E. Maricau, K.U. Leuven 15 Process Variability [Bernstein et al. IBM Journal 2006] Random dopant fluctuations Line edge roughness [Pelgrom, JSSC 89]

16. CAS-FEST 2010 © E. Maricau, K.U. Leuven 16 Hot Carrier Degradation  channel hot carrier A well known phenomenon (>25 years) Interface traps due to impact ionization Dominant for NMOS in saturation » high V DS » high V GS Impact at device level »  V TH, ,  g o n+n+ n+n+

17. CAS-FEST 2010 © E. Maricau, K.U. Leuven 17 Hot Carrier Degradation  ESAT-MICAS model [Maricau ESREF08] Based on Reaction-Diffusion (RD) model Includes all important transistor parameters (Vgs, Vds, L, T) DC and AC voltage stress

18. CAS-FEST 2010 © E. Maricau, K.U. Leuven 18 Hot Carrier Degradation [Maricau ESREF08]

19. CAS-FEST 2010 © E. Maricau, K.U. Leuven 19 Negative Bias Temperature Instability  new phenomenon (<5 years)  important for pMOS  traps due to electro-chemical reaction with SiH  large V GS  temperature activated  relaxation phenomenon Interface traps: permanent part Oxide traps: recoverable part  Impact at device level  V TH, ,  g o p+p+ p+p+

20. CAS-FEST 2010 © E. Maricau, K.U. Leuven 20 Negative Bias Temperature Instability  ESAT-MICAS model [Maricau EL10] Model permanent (P) and recoverable (R) component Includes important transistor parameters (Vgs, T) DC and AC voltage stress

21. CAS-FEST 2010 © E. Maricau, K.U. Leuven 21 Negative Bias Temperature Instability [Maricau EL10]

22. CAS-FEST 2010 © E. Maricau, K.U. Leuven 22 Time Dependent Dielectric Breakdown  PMOS and NMOS  Statistical phenomenon  Gate current increases  high V GS  soft BD – I g noise  hard BD – k  gate resistance t SBD t HBD

23. CAS-FEST 2010 © E. Maricau, K.U. Leuven 23 Time Dependent Dielectric Breakdown  Soft Breakdown 65nm technology Example SBD: » 1V gate stress » 10 year stress time Time to BD follows a Weibull distribution [Maricau DATE11]

24. CAS-FEST 2010 © E. Maricau, K.U. Leuven 24 Transistor Reliability in Sub 65nm CMOS [Gielen DATE11]  Aging becomes worse EOT reduces » E eff increases New materials (High-k) » PBTI SiO2 Interfacial Layer » NBTI, HC, TDDB remains

25. CAS-FEST 2010 © E. Maricau, K.U. Leuven 25 Transistor Reliability in Sub 65nm CMOS  Everything becomes stochastic NBTI PBTI Hot Carrier degradation Soft Breakdown Process variability [Huard, IRPS08]

26. CAS-FEST 2010 © E. Maricau, K.U. Leuven 26 Bias Temperature Instability [Gielen DATE11]  Stochastic BTI model Individual charges can change  V TH Poisson distribution for number of trapped charges (N=mean number of traps) Exponential distribution for the impact of an individual defect (  = average impact)  V TH =f(Vgs,T)  V TH )=f(1/(WL))

27. CAS-FEST 2010 © E. Maricau, K.U. Leuven 27 Transistor Model [Maricau, ESREF08, DATE11]

28. CAS-FEST 2010 © E. Maricau, K.U. Leuven 28 Contents  Introduction  Reliability Effect Modeling  Reliability Simulation  Reliability-aware Design  Conclusions

29. CAS-FEST 2010 © E. Maricau, K.U. Leuven 29 Reliability Simulation  IC Analysis: Performance(t)?  Time-varying stress (Analog!)  Gradual OP shift (iteration in software)  Similar to ELDO and RelXpert [Maricau, DATE09, TCAD10]

30. CAS-FEST 2010 © E. Maricau, K.U. Leuven 30 Example: LC-VCO  5 GHz low phase noise High output swing High LC-tank Q-factor Protective gate-capacitors (DC-bias not shown) UMC 90nm

31. CAS-FEST 2010 © E. Maricau, K.U. Leuven 31 Nominal Simulation  AC simulation shows sudden V out degradation (due to g o degradation)  No frequency degradation  Failure due to Hot Carrier damage

32. CAS-FEST 2010 © E. Maricau, K.U. Leuven 32 Variability awareness?  Process variability introduces stress variability  Transistor aging + process variability = yield(t) T fail,nom T fail,20 % [Maricau TCAD10]

33. CAS-FEST 2010 © E. Maricau, K.U. Leuven 33 Variability Aware Reliability Simulation Factor Space (Process Variability) Performance Space (Circuit Dependent) Yield (Application Dependent) Deterministic Reliability Simulation ?

34. CAS-FEST 2010 © E. Maricau, K.U. Leuven 34 Performance Space Exploration Option 1: Monte-Carlo  Monte-Carlo loop around nominal reliability simulation  Chi-square goodness-of-fit to find a good PDF at every time-point  Accurate but very slow Option 2: Design of experiments (DoE) + Response Surface Model (RSM)  Goal: faster while maintaining accuracy  Means  DoE: make every sample count!  Monte-Carlo on RSM ?

35. CAS-FEST 2010 © E. Maricau, K.U. Leuven 35 Variability Aware Reliability Simulation Factor Space Exploration Screening Linear model Detect interactions Regression Interactions Weak non-linear effects Polynomial RSM Residual analysis Error estimation [Maricau DATE 10]

36. CAS-FEST 2010 © E. Maricau, K.U. Leuven 36 Stochastic Reliability Simulation  Stochastic Unreliability Effects Breakdown BTI in sub 45 nm Technologies  Circuit Aging Time-dependent transistor parameter shift » e.g.  V TH =f(t) Time-dependent transistor parameter standard deviation » e.g.  (V TH )=f(t)

37. CAS-FEST 2010 © E. Maricau, K.U. Leuven 37 Stochastic Reliability Simulation

38. CAS-FEST 2010 © E. Maricau, K.U. Leuven 38 Stochastic Reliability Simulation  Treat aging effects as a time-dependent factor Spatial factors Time-dependent factors  More factors means longer simulation time! Factor minimization based on sensitivity analysis [Maricau DATE 11]

39. CAS-FEST 2010 © E. Maricau, K.U. Leuven 39 Example: 65nm CMOS IDAC

40. CAS-FEST 2010 © E. Maricau, K.U. Leuven 40 Simple Current Mirror

41. CAS-FEST 2010 © E. Maricau, K.U. Leuven 41 Sensitivity Analysis Current Mirror  8 transistors + 2 resistors: 37 factors  After sensitivity analysis: 25 factors

42. CAS-FEST 2010 © E. Maricau, K.U. Leuven 42 6-bit Current-Steering DAC  Transimpedance amplifier Not sensitive to aging  Current sources SBD effects cause time-dependent transistor mismatch

43. CAS-FEST 2010 © E. Maricau, K.U. Leuven 43 IDAC Simulation Results [Maricau DATE 11]

44. CAS-FEST 2010 © E. Maricau, K.U. Leuven 44 Contents  Introduction  Reliability Effect Modeling  Reliability Simulation  Reliability-aware Design  Conclusions

45. CAS-FEST 2010 © E. Maricau, K.U. Leuven 45 Design for Failure Resilience  Intrinsically robust circuits Worst-case overdesign to account for aging effects Consumes extra power and area  Self-healing circuits adapt circuits at run-time to compensate for the degradation » reconfiguration or tuning of the circuit » digital calibration required performance is kept, although degradation is present Tools are needed to analyze the circuit at design time and to find adequate solutions!

46. CAS-FEST 2010 © E. Maricau, K.U. Leuven 46 Intrinsically Robust Circuits [Maricau DATE 10]

47. CAS-FEST 2010 © E. Maricau, K.U. Leuven 47 Self-healing Circuits  Run-time adaptability adapt circuits at run-time to compensate for the degradation » reconfiguration or tuning of the circuit required performance is kept, although degradation is present concept of Knobs and Monitors:

48. CAS-FEST 2010 © E. Maricau, K.U. Leuven 48 Example: A High-Voltage Line Driver  Output driver overview:  Equivalent Model: [Serneels, ISSCC2007]

49. CAS-FEST 2010 © E. Maricau, K.U. Leuven 49 Example: A High-Voltage Line Driver  Guarantee minimum efficiency  Breakdown monitors [De Wit DRVW08]

50. CAS-FEST 2010 © E. Maricau, K.U. Leuven 50 Example: A High-Voltage Line Driver  Measurements are ongoing (65nm CMOS)

51. CAS-FEST 2010 © E. Maricau, K.U. Leuven 51 Other Work  Acar did something similar for a output driver [ISSCC 2008]  Singh [Singh, CICC 2010], Karl [Karl, VLSI 2009] and Keane [Keane, JSSC 2010] proposed in-situ aging monitors for BTI, HCI and TDDB  Industry DARPA: “Self-healing mixed signal integrated circuits (HEALICs)” project. [Karl ISSCC08]

52. CAS-FEST 2010 © E. Maricau, K.U. Leuven 52 Conclusions  Spatial and temporal reliability are an issue in nanometer CMOS analog IC design  Accurate modeling and efficient CAD tools are needed to assist the designer Design for reliability Increase design margins  Solutions have been proposed Accurate transistor aging models for BTI, HC and TDDB effects Efficient Circuit Reliability Simulator methods Design solutions » Robust design » Self-healing circuits