1. Timing and Constraints “The software is the lens through which the user views the FPGA.” -Bill Carter

2. Outline Basic Timing (comb. and sequential) Block timing models –LUTs –BRAM –Multipliers Some standard design timing tricks Constraints –Timing –Geometric (pinning & arrangement –Combinations Best tools –Experience –Insight

3. Propagation Delay LUT Tpd is called “Tilo”

4. Flop Timing

5. LUT Logic Timing Parameters

6. Basic LUT Logic Timing

7. Distributed RAM Timing Model

8. Dist. RAM Parameters

9. LUT SRL Timing Model

10. SRL Timing Parameters

11. LUT w. Carry Chain Focus

12. Carry Chain Timing

13. BRAM Timing Model

14. BRAM Timing Params

15. Multiplier Model & Delay Variation

16. Multiplier Timing Params

17. Routing Delays FPGA datasheets do not give details on routing delay. Hence: –Routing delays not known to designer until design is placed and routed –Delays for early silicon are frequently still under analysis –Software maintains best source for the real timing FPGA datasheets do provide times associated with incremental silicon blocks

18. Virtex style logic tile Comment: CLE with IMUX and OMUX is what we Call the “CLB”

19. What you may find inside the Interconnect block Little black splotches Are muxes or little PIPs to make selectable Attachments….

20. Some standard timing tricks Load splitting (aka fanout reduction) –Identify sites driving large number of loads –Insert buffered version of the signal with multiple buffers each handling a piece of the total load –Result usually faster Pipelining –Insert flip flop stages to reduce setup time restrictions –Increases clocking speed, at expense of added latency

21. Pipelining Idea

22. Pipeline solution Each flip stage can operate at faster Rate than before, but result goes valid After TWO clocks.

23. Constraints More options than we will discuss today High level, global constraints = big payoff Will compare a couple of designs across multiple constraints/combinations to illustrate: –32 bit adder (inherent internal constraint) Combinational suggests tPD constraints –32 bit shifter (very malleable) Sequential suggests Fmax or cycle constraints

24. Spartan 3S50 TQ144

25. Big Adder module Big_Adder1( input [31:0] A, input [31:0] B, output [32:0] SUM ); assign SUM = A + B; endmodule

26. Big Adder (unconstrained)

27. Adder with 20 nsec tPD constraint

28. Change constraint Original unconstrained looks ~same as the nominal 20 nsec constraint. 20 nsec constraint came in at 11.83 nsec. Push it down a little, to say 11 nsec and see what happens……

30. Adder with 11 ns constraint originalnew

31. Timing Improvement Wizard Screen 1

32. TIW Screen 2

33. TIW Screen 3 Bad news ~78% of the Delay is due to logic Suggests need for faster part

34. Note Several bits Are out of spec

35. Interesting… Faster design Meets time Without Shift to right? Comment: Recompiled On -5 version (original =-4)

36. Comments Free pinning, free routing gave a result and revealed that 11.83 nsec possible Free pinning, constrained to 11 nsec revealed 11 nsec is NOT possible (for -4 part) ~78% time spent in silicon delay ~22% time spent in routing delay Faster part (-5) hits 11 nsec, with centered design. Faster part won’t hit 10 nsec when constrained (please experiment for yourself!)

37. “Big_Shifter” Code module Big_Shifter( input C, input ALOAD, input SI, input [31:0] D, output SO ); reg [31:0] tmp; always @(posedge C or posedge ALOAD) begin if (ALOAD) tmp = D; else begin tmp = {tmp[30:0], SI}; end assign SO = tmp[31]; endmodule

38. Big Shifter (unconstrained)

40. Run Failed….chunk of PAR report

41. Revised Constraints

42. Revised layout

43. Constraint revised again

44. Didn’t run: PAR report advice

45. Hmmm…based on slack revise to:

46. PAR report from revised setup/hold times Bingo!

47. clock Clock net Serial in Serial out

48. From “FloorPlan IO Pre-Synthesis” Just defining at the BANK level (versus explicit PADs)

49. Placing half pins on Bank 0 Shifted the design around But still met timing…..

50. Closing Comments The ISE constraints guide is online It has timing, placement, grouping, relational and synthesis level constraints for both VHDL and Verilog MOST designers prefer to have a design.ucf file as a separate item. Best results most often by writing in RTL with.ucf file Best approach is to experiment using small designs to see what the results are –Examine various reports –Look at “world view” –Pay attention to advice from S/W

51. Footnote: WebPack 11.1 v. of shifter