1. INRIA Aoste group : General Introduction to other talks R. de Simone

2. Embedded Reactive applications Data/signal processing, streaming, etc Data-flow computations + control-flow modes Rather static software architecture (little dynamic creation and recursive invocation)  components with ports rather than objects with methods Software design with “hardware-inspired” paradigms …but less stringent time constraint (traditional hardware single clock, cycle accurate RTL) … … but new ESL (Electronic-System Level) hardware design calls for GALS and multiclock/polychronous extensions, event-based vs time-based communications, and other “ software-inspired ” features with a relaxed, “logical” time view.

3. Example specification formalisms Matlab/Simulink, Scilab/Scicos, StateCharts… Synchronous Reactive Formalisms (Esterel, Signal, Lustre) and polychronous/multiclock GALS N-synchronous extensions Nested loops with “affine bounds” (finite control) and similar formats MMAlpha, Array-OL, PicoExpress, StreamIt, Compaan, AutoPilot, … Process Networks and Data Flow domains Event/Marked Graphs, Free-choice Nets (conflict free models) Synchronous, Boolean, CycloStatic, CycloDynamic DFs (Ptolemy)

4. Hardware trends (our naïve view) (Previously) more and more complex schemes to exploit Instruction-Level Parallelism, and beyond (superscalar/VLIW, out-of-order, speculation, prediction,…) Multicore, multiprocessor-on-a-chip era Regular interconnect fabric, predictability sought in latencies Regular memory structure sought physically distributed but logically shared Second-generation On-chip network architectures (Tilera, Ambric, Trips, Tsar?,…) PRET machine (Edwards/Lee/Patel et al) New hardware/system platform architecture seems to match better the reactive embedded application scheme. True ?

5. General approach Use classical representation diagrams Components with ports for hierarchical structure Hierarchical state/activity diagrams for behavior Allow various logical time structures, and progressive refinement Use UML/SysML (might as well benefit from semantic elusiveness and “variation points”) Provide general means for time relations as stereotypes: Clock Constraint Specification Language (CCSL) in MARTE profile Study general allocation mechanisms (and related algorithms), where: allocation = physical distribution/placement + temporal scheduling

6. Example: Gajski’s TLM Time granularity for communication/computation objects can be classified into 3 basic categories. Models B, C, D and E could be classified as TLMs. copyright 2003 Dan Gajski and Lukai Cai

7. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow if unitary latencies and channel markings

8. Asynchronous version nodes fire independently (local clocks)  Event Graphs Communication channels: marked places (abstract buffers) Soundness: no token-free cycle Finite capacity buffers can be modeled by place capacity, itself replaced by adding backward flow-control places and edges. f g

9. Synchronous version Unitary latencies, one token in each link tokens never absent, full throughput absence handled as additional value nodes fire simultaneously (on a global clock) Communication channels: latch registers (or simple wires) Soundness: no combinatorial cycle f g

10. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow static scheduling Multiclocked k- periodic synchronous retiming/recycling Marked/Event Graphs with latencies on computation (transition) communication (channel)

11. Latency-equalized static scheduling throughput 3/5 unit (integer) latency fractional (<1) latency register transportation nodes Relay-stations

12. final resulting static scheduling (11010) (10101) (10110) (01101) (01011) (11010) [00100]

13. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow static scheduling Multiclocked k- periodic synchronous retiming/recycling Marked/Event Graphs with latencies on computation (transition) communication (channel) KEG/KRG Kahn- extended EGs K- periodic Routed Gs cyclo-static BDF Synchr. DataFlow Process Networks rerouting axiomatic transformations

14. Selects up across Merges

15. A MoCC-ing view Basic monoclock synchronous (circuits) Purely asynchronous Process Networks (Marked/Event Graphs) uniform data flow static scheduling Multiclocked k- periodic synchronous retiming/recycling Marked/Event Graphs with latencies on computation (transition) communication (channel) KEG/KRG Kahn- extended EGs K- periodic Routed Gs cyclo-static BDF Synchr. DataFlow Process Networks rerouting axiomatic transformations MARTE Time Model: Provide a laybed for all this (and more ?)

16. Presentations breakdown Charles André : MARTE CCSL at work TimeSquare Julien Boucaron: Latency-Insensitive Design and static scheduling K-Passa Jean-Vivien Millo: Scheduling optimization and balanced regimes Anthony Coadou: Predictable/deterministic control introduction and relation to other models Jean-François le Tallec ?: … Aamir Mehmood: UML MARTE subprofile for IP-XACT

17. Next ? Mix the routing and the scheduling ? Look beyond the rational/regular/k-periodic finite predictable /computable case ? …