1. Optimization of Through Si Via Last Lithography for 3D Packaging
 Warren W. Flack, Robert Hsieh, Gareth Kenyon
Ultratech, Inc.
John Slabbekoorn, Bert Tobback, Tom Vandeweyer, Andy Miller
IMEC

2. Outline Introduction Lithography Experimental Methods Metrology
TSV Process; Alignment System
Experimental Methods
Metrology
Targets; Tool Induced Shift
Results
Summary

3. Outline Introduction Lithography Experimental Methods Metrology
Results
Summary

4. Introduction
Scaling the diameter of the TSV is a major driver for improvement in system performance and cost.
Reducing the size of via landing pads provide significant advantages for device design and final chip size.
Current via last diameters are approximately 30µm and are being scaled to 5µm and beyond.
With smaller TSV diameters, the back-to-front overlay becomes a critical parameter because via landing pads on the first level metal must be large enough to include both TSV critical dimension (CD) and overlay variations.
The goal of this study is to demonstrate <750nm back-to- front overlay capability as a stepping stone for next generation TSV scaling
TSV adoption is being driven forward by a smaller package size-to-function ratio, higher operating performance, lower packaging cost along with a reduced power consumption. It would appear, then, that the 3D Package market and TSV adoption go hand-in-hand.
TSV technology, then, is a key enabler for performance improvement in next generation 3D Packaging. There are three current methods for TSV generation, under the guises of via-first, middle & last. Creating a TSV-last requires back-side wafer processing that can adopt industry standard Damascene (C4) processing that, in turn, can be carried out at foundry or OSAT alike.
The TSV lithography is a crucial step with respect to the final device yield & performance and scaling the TSV will improve performance and cost. 3D TSV implementation alleviates interconnect delay, through conservation of wiring length, creates superior bandwidth performance, power management and device latency. With current standards at 30um diameter, TSV’s are being scaled to 5um with a potential for <2um in the mix. A reduction in via, brings a desirable reduction in landing pad size. But as one would expect, nothing good comes for free - right!? The reduction increases the onus on accuracy of back to front alignment to accommodate overlay variation as well as CD variation of the TSV. 3D

5. TSV-Last Process
TSV scaling permits scaling of the landing pad & impacts device design
Sizing of the landing pad impacts overlay budget as less real estate is available for placement inaccuracy 1 2 3 4 5
Representation of complete TSV-last process
Front-end and Back-end processing
Temporary bonding and thinning
TSV-last lithography
TSV etch
TSV filling, RDL and de-bonding from carrier.
A physical limitation to TSV’s is the associated Keep Out Zone (KOZ). This can be defined as an area around the TSV where active devices cannot be placed due to localised stress creating changes in the electrical performance, for example. It is, therefore, a logical desire to reduce this region and permit more active area. For via middle processes, KOZ scales with the square of TSV diameter and reduces with lower aspect ratios. Via last processes have yielded reduced KOZ as the manufacturing processes yield a reduced stress (Takeda & Aoki, 2014 IEE Int.).
Filled TSV
Landing Pad

6. Outline Introduction Lithography Experimental Methods Metrology
Results
Summary

7. Alignment System IR transmits through silicon
Top directed illumination allows for flexible placement of targets on the wafer
Off axis IR camera implemented on stepper
Measure XY positions of two features at different Z heights
Together these features make up the Dual Side Align (DSA) alignment system
Various methods for viewing embedded alignment targets have been developed over the years but the top IR illumination method depicted here provides practical advantages for a stepper. Namely, direct imagery and illumination, no chuck design constraints meaning free dispersal of alignment targets.
Go on to describe the picture…
Remember; Wafer side convention, IR target requires reflective to IR material – metal for example.

8. Outline Introduction Lithography Experimental Methods Metrology
Results
Summary

9. Experimental Methods
Alignment requirement is that TSV etching will land completely on METAL1 pads for the 5 x 50µm TSV process
Two photo-resists were examined with thickness at 7.5µm:
gh-line Novolak based resist requiring 1250mJ/cm2
i-line Chemical Amplified Resist (CAR) requiring 450mJ/cm2
Wafers are exposed, developed and then measured for overlay; Corrections are then made to optimize the alignment using a point sampling plan
Once optimized, a less dense (115 point) sampling plan is used to monitor process stability
I - line resist was examined for a couple of reasons. One is for it’s capability with the plating process. Another , was for thru’put and thermal capability. A higher energy will lead to thermal stress in the materials and the tool that can impact performance.

10. 300mm Sampling Maps Dense sample of 184 steps, 920 total points
Reduced sample of 23 steps, 115 total points
The reduced sample removes edge sites; 300mm wafer

11. Example Vector Plot
Once gathered, data is calculated and displayed as a vector plot
The arrow scale (µm) is indicated in the top left corner and wafer notch is represented by the green spot.
5 points per field
Creates a wafer map that gives rise to visual trends…
Are the trends real… Or is it the metrology itself that is creating the effects…

12. Outline Introduction Lithography Experimental Methods Metrology
Results
Summary

13. Metrology Field Layout
The red arrows indicate DSA-SSM overlay verification locations.
TSV-last process development reticle
DSA-SSM metrology target for 5µm diameter TSV’s. Process rules dictate all vias must be the same size, and so a target has to be integral to the process, but unique.
All processing was performed on 300mm wafers, building the structures described in the TSV process slide discussed earlier (slide 3). 5 metrology sites were defined for each shot. Process rules dictate that any feature used for metrology has to be bound within those rules. In this case, the targets needed to be constructed from 5um vias. However this reticle set does support 2um vias and targets were also constructed for this technology – not shown here.
Stepper Self Metrology (SSM) target

14. Metrology in Action
@ 0 µm focus
@ -50 µm focus
Describe targeting.
With these particular wafers, the embedded target is 50um into the silicon film stack & the photo-resist target is at 0um. The stage moves in X, Y & Z capturing and storing values for each target.
Photo-resist metrology target is defined as a cluster of 5µm TSV’s
Reference metrology target is defined as a large circular metal pad
The stage captures each target at a different Z heights to obtain in-focus images. Alignment error is calculated by the relative position of the targets

15. Tool Induced Shift (TIS)
Tool Induced Shift (TIS) is an apparent alignment offset caused by metrology
Several parameters can influence TIS:
Tilt in camera or wafer
Non-symmetric Illumination
Photo-resist processing
camera
photoresist
Thinned Si wafer
The concept of Tool Induced Shift (TIS) provides a method to compensate for systematic measurement errors.
Describe imagery of slide
The basic idea is that two measurements taken at 0 and 180 degree wafer orientations can be represented as two components of error
a TIS error component which is independent of orientation, and
a characteristic or “actual” measurement which rotates with the wafer.
The image shows a tilted camera viewing a pattern in photo-resist and a buried metal reference.
The resist pattern appears shifted from the viewpoint of the camera with respect to the vertical
oxide
reference
glue
Si Carrier

16. Concept of TIS TIS can be conceptualized as a vector diagram
TIS is an inherent error exhibited in all metrology systems
Apparent error is actual error plus TIS
The apparent error (raw measurement) is the sum of actual error and TIS.
TIS can be visualised as a vector plot as seen here. Describe the vector plot…

17. Calculation of TIS
For a 180 degree rotation of the wafer the error associated with the wafer rotates, but the TIS component is stationary.
The actual error can now be determined from the difference between the 0 and 180 degree measurement, and the TIS can be determined from the sum.
TIS is typically measured once per lot of wafers by rotating one sample wafer by 180 degrees and re-measuring. Comparing the 0 degree versus the 180 degree will reveal the actual overlay offsets and the TIS.

18. TIS Equations
The basic TIS calculations are summarized in equations (1) through (4). Subscript “0” denotes the zero degree orientation measurement, and “180” denotes the 180 degree orientation measurement.
Essentially, the actual error is a subtraction of values divided by 2, whereas the TIS is and addition of values divided by 2

19. Outline Introduction Lithography Experimental Methods Metrology
Results
Summary

20. Measurement Repeatability
Each die on one wafer (with 115 die per wafer) was measured 5 separate times
Average 3σ is 30nm in X and Y
This is consistent with the requirement for >750 nm overlay performance
First of all, is it the metrology itself that is creating the effects that we observe? By performing a repeatability check of the same wafer, loaded, unloaded, measuring the same dies, a sanity check is delivered.

21. TIS Estimate
Vector Plot depicting field point TIS estimate, derived from 0 degree and 180 degree measurements using equations 1 and 2.
Very consistent & repeatable, indicates robustness
Wafer #5 of 10 wafer production run. The average TIS offset is:
X = -155nm; Y = -453nm
This result is generated by adding the 180 degree measurement from the 0 degree measurement and dividing by two. It is important to note that the sign for X & Y flips with rotation and this is maintained in any follow-up calculations. Initially, all wafers were measured for TIS, but the results were comparable from wafer to wafer, within the reported repeatability, and so it is not necessary to perform a TIS for every wafer. One from the lot can be done, typically at the end.

22. Example Corrected Overlay
Calculation of corrected Overlay data from 0 degree and 180 degree measurements using equations 3 and 4
Wafer # 4 of 10 wafer production run. The 3σ is:
X = 658nm; Y = 515nm
Corrected Data

23. Lot Overlay Data Dense Lot : X 3σ = 0.765 Y 3σ = 0.599 Reduced Lot:
Initial data was used to offset the linear terms for the process job on the stepper. System correction to a known reference occurs prior to the job run in order to minimise small linear and non-linear (for example thermal) changes that occur to the system stage.
Lot overlay data shown is after TIS correction of the mean
Reduced sampling shows a smaller Y 3σ compared to dense sampling
The even and odd wafers show different repeating 3σ signatures

24. Overlay Data Analysis
An analysis of the X errors reveals non-linear errors.
Characterized by examining the residuals. These are the theoretical errors that remain after optimizing all possible linear grid and intra-field terms.
Denser sampling plan shows a larger X and Y 3σ
The non-linear error signature, and having more sites near the wafer edge for the dense sampling plan contributes to the difference between the two sampling plans.
The non-linear error signature, and having more sites near the wafer edge for the dense sampling plan contributes to the difference between the two sampling plans.

25. Residual Vector Plot Even Wafer Odd Wafer
Non-linearity is readily visualised using the vector plots
Non linearity errors cannot be corrected using traditional stepper terms such as scale, translation and magnification & are what remains

26. Lot Residual Error Analysis
A closer look yields a characteristic, alternating pattern, not attributable to the stepper.
Investigation into the root cause of the odd/even error source is ongoing.
Residuals can be random errors or non-correctable patterns. Describe slide data. (Odd wafers have a much higher X residual.) This is an example of an effect that cannot be easily identified without automated in-line metrology.
Odd Wafers (1,3,5,7,9)
Per wafer residuals 3σ
Even Wafers (2,4,6,8,10) X Y
0.699
0.348
0.464
0.304

27. Reducing Non-Linear Errors
Non-linear effects can be approached in various ways depending on the stability of the signature
For thinned substrates, significant distortions may come from processing steps other than lithography
Subdividing the wafer map into multiple alignment zones provides a flexible method to account for non-linear effects, because it allows for independent mapping and optimization of each zone

28. Multi-Zone Alignment Each zone can be independently mapped
Each zone can have independent linear corrections

29. Multi-Zone Results
Comparison of standard alignment mapping and four quadrant mapping for an even and odd numbered wafer.
Raw data overlay is not greatly improved, but gains are made in per wafer/quadrant residual, particularly with the odd numbered wafers
Even Wafer
Run Type
Raw Data
Wafer Residual
Quadrant Residual
X 3
Y 3
Standard Alignment
0.658
0.515
0.475
0.293
0.230
0.278
Four zone mapping
0.664
0.557
0.332
0.358
0.187
0.264
Odd Wafer
Run Type
Raw Data
Wafer Residual
Quadrant Residual
X 3
Y 3
Standard Alignment
0.859
0.543
0.715
0.362
0.293
0.278
Four zone mapping
0.693
0.553
0.338
0.359
0.201
0.266
There is no great improvement in the raw data, but improvement in the residual data indicates a better fit to non-linear errors inherent to the wafer.

30. Summary
Scaling of TSV’s in the TSV-last process requires tighter specs on overlay.
Direct verification of TSV litho to the embedded reference layer is enabled by using the DSA alignment system combined with dedicated analysis software.
Non-linear effects on alternating wafers can be a limiting factor in the achievable overlay performance.
Gains are possible in the areas of wafer order effects & non- linear wafer signature using zonal alignment to minimize residual error
On good quality wafers the overlay performance is better than 750nm which is required for less than 5µm diameter TSV’s